Patents by Inventor Yoshitsugu Yamamoto

Yoshitsugu Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6570390
    Abstract: A method of measuring a surface leakage current includes applying a voltage between a pair of electrodes, which are apart from each other on a sample surface, during a predetermined period of time. A region of the sample surface between the pair of electrodes is irradiated by energy rays during an irradiation period of time which is within the voltage application time. The energy rays may be lasers, ultraviolet rays, X-rays or an electron beam. A current flowing between the pair of electrodes is measured during the voltage application time. The energy rays irradiation causes a surface leakage current, which is caused by adhered substances, to start to flow, and when the adhered substances have been eliminated perfectly, a relatively large current caused by the adhered substances disappears. Perfect elimination of the adhered substances can be verified by confirming that the relatively large current has disappeared.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: May 27, 2003
    Assignees: Rigaku Corporation, Mitsubishi Denki Kabushiki Kaisha
    Inventors: Taisei Hirayama, Koichiro Ito, Ryo Hattori, Yoshitsugu Yamamoto, Yoshihiro Notani, Shinichi Miyakuni
  • Patent number: 6043520
    Abstract: A hetero-junction bipolar transistor having high reliability wherein a ballast resistance is exactly controlled and deterioration in current stability is eliminated. A GaAs ballast resistor layer is provided in a hetero-junction bipolar transistor having a GaAs emitter layer, an InGaP spacer layer, and a GaAs base layer, preventing a notch from being formed in the conduction band at the interface of the emitter layer and the ballast resistor layer, exactly controlling the ballast resistance. The AlGaAs layer is prevented from trapping impurities and the current stability is prevented from deteriorating.
    Type: Grant
    Filed: September 18, 1998
    Date of Patent: March 28, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshitsugu Yamamoto, Ryo Hattori
  • Patent number: 6037242
    Abstract: A method of preparing an AlInAs/GaAs hetero-structure includes forming an Al.sub.1-x In.sub.x As (0<x<1) buffer layer in an amorphous state on a GaAs substrate, annealing the amorphous buffer layer to crystallize the buffer layer into a single crystal buffer layer, and forming a single crystal Al.sub.1-x' In.sub.x' As (0<x'<1) active layer on the single crystal buffer layer.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: March 14, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Norio Hayafuji, Yoshitsugu Yamamoto
  • Patent number: 5874753
    Abstract: In a field effect transistor including active layers having a heterojunction structure with at least two different semiconductor materials, a layer for supplying electrons is disposed opposite a drain electrode, in contact with a region of the active layers including a dopant impurity producing n type conductivity. Therefore, degradation of the electrical characteristics caused by trapping of electrons in a drain ohmic contact layer due to fluorine diffusing into the semiconductor layers is suppressed by supplying electrons from the layer opposite the drain electrode, thereby improving reliability of the field effect transistor including the heterojunction structure.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: February 23, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Norio Hayafuji, Yoshitsugu Yamamoto
  • Patent number: 5811843
    Abstract: A field effect transistor includes a semi-insulating III-V compound semiconductor substrate; a channel layer disposed on the substrate; an n type electron supply layer disposed on the channel layer and comprising a mixed crystalline compound semiconductor layer including AlAs; an n type ohmic contact layer disposed on the electron supply layer; source and drain electrodes disposed on the ohmic contact layer; an opening in a region between the source and drain electrodes penetrating the ohmic contact layer; a gate electrode disposed in the opening and making a Schotty contact; and a surface protection film of a semiconductor material free of Al, In, and As, covering the opening except where the gate electrode is present. Fluorine is prevented from getting into the electron supply layer with no increase in transconductance or source resistance by providing a layer between the source and a channel, and between the gate and the channel.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: September 22, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshitsugu Yamamoto, Norio Hayafuji
  • Patent number: 5796127
    Abstract: A method of fabricating a semiconductor device includes forming a first mixed crystal semiconductor layer of AlAs and InAs; applying a solution containing a material easily combining with fluorine to the surface of the first mixed crystal semiconductor layer exposed to the atmosphere so that the material combines with fluorine that sticks to the surface of the first mixed crystal semiconductor layer; and annealing the first mixed crystal semiconductor layer in a vacuum. In this method, since the fluorine on the surface of the first mixed crystal semiconductor layer exposed to the atmosphere combines with the material included in the solution and is removed together with the material, a first mixed crystal semiconductor layer having no fluorine is produced. Therefore, unwanted infiltration of fluorine into the first mixed crystal semiconductor layer is avoided, resulting in a highly reliable semiconductor device with desired characteristics.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: August 18, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Norio Hayafuji, Yoshitsugu Yamamoto, Hirotaka Kizuki
  • Patent number: 5729030
    Abstract: A semiconductor device includes an InP substrate; a channel layer in which electrons, as charge carriers, travel; and an Al.sub.x1 Ga.sub.1-x1 As.sub.y1 P.sub.z1 Sb.sub.1-y1-z1 (0.ltoreq.x1.ltoreq.1, 0.ltoreq.y1<1, 0<z1.ltoreq.1) electron supply layer for supplying electrons to the channel layer. The electron supply layer has an electron affinity smaller than that of the channel layer and is doped with a dopant impurity producing n type conductivity. Since n type AlGaAsPSb is thermally stable, its electrical characteristics are not changed by heat treatment at about 350.degree. C., resulting in a thermally stable and highly reliable HEMT in which the characteristics hardly change with the passage of time during fabrication and operation. Further, a heterostructure including an electron supply layer and a channel layer and having a desired energy band structure is easily produced with a wide degree of freedom in designing the device.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: March 17, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshitsugu Yamamoto, Norio Hayafuji
  • Patent number: 5682045
    Abstract: An Si-doped AlInAs layer and an intrinsic AlInAs layer are successively grown on a semi-insulating InP substrate in a molecular beam epitaxy chamber. The sample is then heat-treated in a nitrogen ambient at 400.degree. C. for 18 minutes so that electrical characteristics of the sample are deteriorated because of the infiltration of fluorine into the Si-doped AlInAs layer. The sample is then placed in the molecular beam epitaxy chamber and reheat-treated in an ultra-high vacuum at 400.degree. C. for seven minutes and the fluorine is removed.
    Type: Grant
    Filed: September 8, 1995
    Date of Patent: October 28, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Norio Hayafuji, Yoshitsugu Yamamoto
  • Patent number: 5677553
    Abstract: A semiconductor device includes a very low dopant impurity concentration InGaAs active layer in which a two-dimensional electron gas is produced, the active layer being disposed on a semiconductor substrate; a very low dopant impurity concentration spacer layer contacting the active layer at a first surface and having an electron affinity smaller than the electron affinity of the active layer; and a very thin InGaAs electron supply layer having a high n type dopant impurity concentration and contacting the spacer layer opposite the active layer. Degradation of device characteristics due to heating of the device is reduced with a result that a thermally stable and highly reliable semiconductor device is easily realized.
    Type: Grant
    Filed: December 19, 1994
    Date of Patent: October 14, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshitsugu Yamamoto, Naohito Yoshida
  • Patent number: 5616181
    Abstract: An MBE apparatus includes a reaction chamber in which a molecular beam of a gas irradiates a substrate for crystal growth; a gas bomb containing the gas; a regulator for reducing the pressure of the gas from the gas bomb; a pressure control apparatus having one or more anode and cathode electrodes, a coil for generating a magnetic field applied to the supplied gas, and a controller for controlling the electric field between the anode and cathode electrodes, the area of the anode and cathode electrodes, and the magnetic field generated by the coil, so that a molecular beam irradiates the substrate with the gas supplied. The supply of the gas may be quickly varied with high reproducibility and high precision. In addition, a semiconductor layer having a uniform carrier concentration can be easily formed on the semiconductor substrate or a semiconductor layer having a uniform composition ratio can be easily formed on the semiconductor substrate.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: April 1, 1997
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshitsugu Yamamoto, Kaoru Kadoiwa