Abstract: An optical waveguide includes a diamond layer including a first surface, a second surface and a diamond layer including a complex defect; a first clad layer in contact with the first surface; a second clad layer in contact with the second surface and including a polarity; and a metal layer in Schottky contact with the second clad layer.

Abstract: A quantum circuit includes a plurality of first optical waveguides and a plurality of second optical waveguides formed on a substrate and each of which includes a single-photon source; a first multiplexer formed on the substrate and configured to condense first photons propagated through the plurality of first optical waveguides; a second multiplexer formed on the substrate and configured to condense second photons propagated through the plurality of second optical waveguides; a branching element configured to introduce the first photons condensed by the first multiplexer and the second photons condensed by the second multiplexer and branch the first photons and the second photons in a first direction and a second direction; a first detector configured to detect the first photons and the second photons branched in the first direction; and a second detector configured to detect the first photons and the second photons branched in the second direction.

Abstract: An apparatus calculates, based on attribute information of a new job and jobs that have been executed, a first similarity level of the attribute information between the new job and the jobs by using a calculation expression, identifies a job whose attribute information is most similar to that of the new job as a first candidate job, and estimates power consumption to be consumed by the new job at power consumption of the first candidate job. The apparatus calculates, for at least one of the jobs, a second similarity level of power consumption between the at least one of the jobs and the new job, identifies a job whose power consumption is most similar to that of the new job as a second candidate job, and adjusts the calculation expression to increase the first similarity level to be calculated between the new job and the second candidate job.

Abstract: An apparatus calculates, based on attribute information of a new job and jobs that have been executed, a first similarity level of the attribute information between the new job and the jobs by using a calculation expression, identifies a job whose attribute information is most similar to that of the new job as a first candidate job, and estimates power consumption to be consumed by the new job at power consumption of the first candidate job. The apparatus calculates, for at least one of the jobs, a second similarity level of power consumption between the at least one of the jobs and the new job, identifies a job whose power consumption is most similar to that of the new job as a second candidate job, and adjusts the calculation expression to increase the first similarity level to be calculated between the new job and the second candidate job.

Abstract: A bias circuit includes a replica circuit for an amplifier circuit using a cascode type inverter, and a generation circuit that generates a bias voltage that causes a drain voltage of an input stage transistor of the amplifier circuit to be a saturation drain voltage, based on an output voltage of the replica circuit, and supplies the generated bias voltage to a cascode element of the amplifier circuit and a cascode element of the replica circuit.

Abstract: A bias circuit includes a replica circuit for an amplifier circuit using a cascode type inverter, and a generation circuit that generates a bias voltage that causes a drain voltage of an input stage transistor of the amplifier circuit to be a saturation drain voltage, based on an output voltage of the replica circuit, and supplies the generated bias voltage to a cascode element of the amplifier circuit and a cascode element of the replica circuit.

Abstract: A storage apparatus includes a physical memory including a plurality of first memory lines a part of which are assigned consecutive addresses and the rest of which are put into an unassigned state where no address is assigned and a second memory line assigned one of the consecutive addresses. The storage apparatus determines based on an address whether a write access to the physical memory is a write access to a first memory line or the second memory line, counts the numbers of times the first memory lines are written and the number of times the second memory line is written, and uses, when the total sum of the counted numbers of times exceeds a threshold, a first memory line in the unassigned state for swapping the address assigned to the second memory line with one of the addresses assigned to the part of the first memory lines.

Abstract: A reception circuit includes: a plurality of block circuits that each include a phase control circuit that controls a phase of a first clock, and a plurality of internal circuits that are driven by a second clock generated based on the phase-controlled first clock, wherein the phase control circuit in each of the block circuits is controlled by means of a control signal from an operation phase control circuit in such a way that an error rate for reception data due to the plurality of block circuits decreases.

Abstract: A communication system includes: a plurality of lanes; a plurality of transmission circuits respectively outputting data to the lanes in accordance with a transmission clock; and a plurality of reception circuits respectively receiving data from the lanes, each reception circuit includes: a clock data recovery circuit extracting own clock information from received data: a clock information switch circuit selecting either one of the own clock information of the reception circuit or another own clock information of an another reception circuit; a phase shifter generating a phase adjusted clock from a common reception clock source in accordance with clock information selected by the clock information switch circuit; and an input circuit taking in transmitted data in accordance with the adjusted clock, and the clock information switch circuit selects the own clock information in a normal operation and selects the another own clock information in an eye-opening measurement operation.

Abstract: A receiving circuit includes: an interpolation circuit that generates, by using an interpolation coefficient, output data including a data point and a boundary point from pieces of input data that are input in chronological order; a detection circuit that outputs a detection signal when the detection circuit detects a phase of the output data by using the boundary point of the output data; a low pass filter that filters the detection signal and generates the interpolation coefficient; and a modulation circuit that modulates, by using a modulation signal having a frequency different from a cutoff frequency of the low pass filter, the interpolation coefficient generated by the low pass filter, and outputs the modulated interpolation coefficient to the interpolation circuit.

Abstract: A communication system includes: a plurality of lanes; a plurality of transmission circuits respectively outputting data to the lanes in accordance with a transmission clock; and a plurality of reception circuits respectively receiving data from the lanes, each reception circuit includes: a clock data recovery circuit extracting own clock information from received data: a clock information switch circuit selecting either one of the own clock information of the reception circuit or another own clock information of an another reception circuit; a phase shifter generating a phase adjusted clock from a common reception clock source in accordance with clock information selected by the clock information switch circuit; and an input circuit taking in transmitted data in accordance with the adjusted clock, and the clock information switch circuit selects the own clock information in a normal operation and selects the another own clock information in an eye-opening measurement operation.

Abstract: A reception circuit includes: a plurality of block circuits that each include a phase control circuit that controls a phase of a first clock, and a plurality of internal circuits that are driven by a second clock generated based on the phase-controlled first clock, wherein the phase control circuit in each of the block circuits is controlled by means of a control signal from an operation phase control circuit in such a way that an error rate for reception data due to the plurality of block circuits decreases.

Abstract: An interpolation circuit includes: a first node to receive a first current; a second node to receive a second current; a third node to receive a third current; a first capacitor circuit including: first capacitors; a first switch to couple one end of each of first capacitors to one of first and second nodes; and a first output coupled to the other end of each of first capacitors; a second capacitor circuit including: second capacitors; a second switch to couple one end of each of second capacitors to one of second and third nodes; and a second output node coupled to the other end of each of second capacitors; and a third capacitor circuit including: a third capacitor whose one end is coupled to the second node; and a third switch to couple the other end of the third capacitor to one of first and second output nodes.

Abstract: A receiving circuit includes: an interpolation circuit that generates, by using an interpolation coefficient, output data including a data point and a boundary point from pieces of input data that are input in chronological order; a detection circuit that outputs a detection signal when the detection circuit detects a phase of the output data by using the boundary point of the output data; a low pass filter that filters the detection signal and generates the interpolation coefficient; and a modulation circuit that modulates, by using a modulation signal having a frequency different from a cutoff frequency of the low pass filter, the interpolation coefficient generated by the low pass filter, and outputs the modulated interpolation coefficient to the interpolation circuit.

Abstract: An interpolation circuit includes: a generation circuit that generates interpolation data from a plurality of pieces of input data, using an interpolation coefficient, among input data inputted in time series including a data point and a transition point; a detection circuit that detects that the input data lacks at the data point; and a coefficient circuit that changes the interpolation coefficient for each given data interval, and skips a position for changing the interpolation coefficient to the transition point when the detection circuit detects the lack of the input data.

Abstract: An interpolation circuit includes: a first node to receive a first current; a second node to receive a second current; a third node to receive a third current; a first capacitor circuit including: first capacitors; a first switch to couple one end of each of first capacitors to one of first and second nodes; and a first output coupled to the other end of each of first capacitors; a second capacitor circuit including: second capacitors; a second switch to couple one end of each of second capacitors to one of second and third nodes; and a second output node coupled to the other end of each of second capacitors; and a third capacitor circuit including: a third capacitor whose one end is coupled to the second node; and a third switch to couple the other end of the third capacitor to one of first and second output nodes.

Abstract: An interpolation circuit includes: a generation circuit that generates interpolation data from a plurality of pieces of input data, using an interpolation coefficient, among input data inputted in time series including a data point and a transition point; a detection circuit that detects that the input data lacks at the data point; and a coefficient circuit that changes the interpolation coefficient for each given data interval, and skips a position for changing the interpolation coefficient to the transition point when the detection circuit detects the lack of the input data.

Abstract: A receiver circuit includes: a first sampling circuit to sample input data in synchronization with a first edge of a sampling clock signal; a second sampling circuit to sample the input data in synchronization with a second edge of the sampling clock signal; a duty-cycle-distortion detection circuit to detect a duty-cycle-distortion amount indicating an error in a duty ratio of the sampling clock signal based on first data which is sampled by the first sampling circuit and second data which is sampled by the second sampling circuit; a correction circuit to correct the first data or the second data to generate first corrected data or second corrected data, respectively, based on the duty-cycle-distortion amount; and a clock data recovery circuit to select data out of the first corrected data and the second data and to recover the selected data.

Abstract: A receiving circuit includes a clock generation circuit that generates a clock signal, an integration filter that stores a signal potential of an input signal and generates a first storage potential in a period in which the clock signal indicates one logic, a first analog-to-digital circuit that converts the first storage potential into a first digital value, and a data determination circuit that determines a logic of the input signal on a basis of the first digital value.

Abstract: A receiver circuit includes: a first sampling circuit to sample input data in synchronization with a first edge of a sampling clock signal; a second sampling circuit to sample the input data in synchronization with a second edge of the sampling clock signal; a duty-cycle-distortion detection circuit to detect a duty-cycle-distortion amount indicating an error in a duty ratio of the sampling clock signal based on first data which is sampled by the first sampling circuit and second data which is sampled by the second sampling circuit; a correction circuit to correct the first data or the second data to generate first corrected data or second corrected data, respectively, based on the duty-cycle-distortion amount; and a clock data recovery circuit to select data out of the first corrected data and the second data and to recover the selected data.