Abstract: A parallel-serial conversion circuit includes: a plurality of data terminals each receiving a data signal; a selection circuit configured to select at least one of the data signals received through the plurality of data terminals; a first latch circuit configured to latch an output from the selection circuit based on a clock signal; a replica selection circuit configured to select one of a plurality of signals and output the selected signal; and a timing-signal generating circuit configured to generate a timing signal for controlling the selection circuit based on the output from the replica selection circuit, wherein the output from the replica selection circuit is latched based on the clock signal.

Abstract: A data transmitting circuit includes a reflection suppressive component generating circuit for generating a reflection suppressive component for suppressing the reflection caused by the discontinuity in the characteristic impedance on a transmission line, and a data output circuit for amplifying the reflection suppressive component and the data to be currently transmitted to a receiving side and outputting them to the transmission line.

Abstract: A data receiving circuit has a data input terminal, a conversion circuit converting an input signal received via the data input terminal, and a decision circuit making a decision on an output of the conversion circuit. The conversion circuit has a demultiplexer converting the input signal into a signal of a lower frequency than the frequency thereof at the data input terminal, and an output of the demultiplexer is obtained at the drain side of each of a plurality of first transistors having a common source.

Abstract: A parallel-serial conversion circuit includes: a plurality of data terminals each receiving a data signal; a selection circuit configured to select at least one of the data signals received through the plurality of data terminals; a first latch circuit configured to latch an output from the selection circuit based on a clock signal; a replica selection circuit configured to select one of a plurality of signals and output the selected signal; and a timing-signal generating circuit configured to generate a timing signal for controlling the selection circuit based on the output from the replica selection circuit, wherein the output from the replica selection circuit is latched based on the clock signal.

Abstract: A semiconductor device includes a first buffer circuit transmitting input signals, a second buffer circuit having a lower drive capability than the first buffer circuit and transmitting the input signals, and a control circuit detecting transitions of the input signals, and activating the first buffer circuit during a period when the input signals make the transitions.

Abstract: A receiving circuit includes a clock generation circuit that generates a clock signal, an integration filter that stores a signal potential of an input signal and generates a first storage potential in a period in which the clock signal indicates one logic, a first analog-to-digital circuit that converts the first storage potential into a first digital value, and a data determination circuit that determines a logic of the input signal on a basis of the first digital value.

Abstract: A charge pump circuit comprises two MOS transistors serially connected between a power supply voltage VDD and ground, a switch SW0, four switches SW1 through SW4, four capacitors C1 through C4, and four switches SW5 through SW8. If a control voltage Vcntl is to be varied, a specific switch SW of the switches SW1 through SW4 is turned on such that a specific capacitor is charged to the power supply voltage VDD. Then, a specific switch SW of the switches SW5 through SW8 is turned on to transfer the electric charge stored in the capacitor to the capacitor of a low-pass filter and thereby the control voltage is controlled at a desired value.

Abstract: A data transmitting circuit includes a reflection suppressive component generating circuit for generating a reflection suppressive component for suppressing the reflection caused by the discontinuity in the characteristic impedance on a transmission line, and a data output circuit for amplifying the reflection suppressive component and the data to be currently transmitted to a receiving side and outputting them to the transmission line.

Abstract: A charge pump circuit comprises two MOS transistors serially connected between a power supply voltage VDD and ground, a switch SW0, four switches SW1 through SW4, four capacitors C1 through C4, and four switches SW5 through SW8. If a control voltage Vcntl is to be varied, a specific switch SW of the switches SW1 through SW4 is turned on such that a specific capacitor is charged to the power supply voltage VDD. Then, a specific switch SW of the switches SW5 through SW8 is turned on to transfer the electric charge stored in the capacitor to the capacitor of a low-pass filter and thereby the control voltage is controlled at a desired value.

Abstract: An input integrating circuit and a differential amplifier circuit are provided in a receiver circuit which samples a pair of differential input signals, detects the levels of said pair of input signals, and latches the detected levels. The above-mentioned input integrating circuit further includes: a pair of input transistors receiving the pair of input signals at respective gates thereof; a switch transistor becoming conducting in response to a sampling clock in a sampling period so as to supply a discharge current to a common source terminal of the pair of input transistors; and a precharge circuit precharging drain terminals of the pair of input transistors in a precharge period. The input integrating circuit discharges the capacitor of the drain terminals by the discharge current in the sampling period succeeding the precharge period. The differential amplifier circuit amplifies the drain terminals of the input integrating circuit.

Abstract: A receiver circuit has a sampling circuit, a buffer circuit, a determining circuit, and a buffer control circuit. The sampling circuit samples an input signal, and the buffer circuit buffers an output of the sampling circuit. The determining circuit determines an output of the buffer circuit, and the buffer control circuit keeps a small input signal dependency of the output of the buffer circuit until carrying out the sampling. Consequently, an inter symbol interference caused by characteristics of a transmission path which poses a problem for receiving a high-speed signal can be invalidated, and therefore the high-speed received signal can be determined with a higher accuracy.

Abstract: In order to enable its testing in the form of including the influence of transmission path, a semiconductor integrated circuit comprising a transmission and a receiving circuit comprises an inserted circuit for receiving an output signal of the transmission circuit and providing the output signal to the receiving circuit; and a switch for connecting the inserted circuit between the output side of the transmission circuit and input side of the receiving circuit, with the transmission circuit comprising a pre-emphasis circuit at a later stage thereof and the receiving circuit comprising an equalizer circuit at a earlier stage thereof, wherein the inserted circuit and switch are connected between an output side of the pre-emphasis circuit and input side of the equalizer circuit.

Abstract: An input integrating circuit and a differential amplifier circuit are provided in a receiver circuit which samples a pair of differential input signals, detects the levels of said pair of input signals, and latches the detected levels. The above-mentioned input integrating circuit further includes: a pair of input transistors receiving the pair of input signals at respective gates thereof; a switch transistor becoming conducting in response to a sampling clock in a sampling period so as to supply a discharge current to a common source terminal of the pair of input transistors; and a precharge circuit precharging drain terminals of the pair of input transistors in a precharge period. The input integrating circuit discharges the capacitor of the drain terminals by the discharge current in the sampling period succeeding the precharge period. The differential amplifier circuit amplifies the drain terminals of the input integrating circuit.

Abstract: A receiver for bidirectional signal transmission, where signals are sent and received in both directions over a signal transmission line, has a signal line, a first hold capacitor, a signal line voltage buffer circuit, a hybrid circuit, and a decision circuit. The signal line is connected to the signal transmission line, the first hold capacitor is used to hold a signal, and the signal line voltage buffer circuit is used to buffer a voltage of the signal line. Further, the hybrid circuit is used to output a received signal by separating the received signal from the signal line voltage buffered by the buffer circuit, and the decision circuit is used to make a decision on the logic value of the received signal separated and output by the hybrid circuit.

Abstract: A data receiving circuit has a data input terminal, a conversion circuit converting an input signal received via the data input terminal, and a decision circuit making a decision on an output of the conversion circuit. The conversion circuit has a demultiplexer converting the input signal into a signal of a lower frequency than the frequency thereof at the data input terminal, and an output of the demultiplexer is obtained at the drain side of each of a plurality of first transistors having a common source.

Abstract: A receiver for bidirectional signal transmission, where signals are sent and received in both directions over a signal transmission line, has a signal line, a first hold capacitor, a signal line voltage buffer circuit, a hybrid circuit, and a decision circuit. The signal line is connected to the signal transmission line, the first hold capacitor is used to hold a signal, and the signal line voltage buffer circuit is used to buffer a voltage of the signal line. Further, the hybrid circuit is used to output a received signal by separating the received signal from the signal line voltage buffered by the buffer circuit, and the decision circuit is used to make a decision on the logic value of the received signal separated and output by the hybrid circuit.

Abstract: A receiver circuit has a sampling circuit, a buffer circuit, a determining circuit, and a buffer control circuit. The sampling circuit samples an input signal, and the buffer circuit buffers an output of the sampling circuit. The determining circuit determines an output of the buffer circuit, and the buffer control circuit keeps a small input signal dependency of the output of the buffer circuit until carrying out the sampling. Consequently, an inter symbol interference caused by characteristics of a transmission path which poses a problem for receiving a high-speed signal can be invalidated, and therefore the high-speed received signal can be determined with a higher accuracy.

Abstract: A receiver for bidirectional signal transmission, where signals are sent and received in both directions over a signal transmission line, has a signal line, a first hold capacitor, a signal line voltage buffer circuit, a hybrid circuit, and a decision circuit. The signal line is connected to the signal transmission line, the first hold capacitor is used to hold a signal, and the signal line voltage buffer circuit is used to buffer a voltage of the signal line. Further, the hybrid circuit is used to output a received signal by separating the received signal from the signal line voltage buffered by the buffer circuit, and the decision circuit is used to make a decision on the logic value of the received signal separated and output by the hybrid circuit.