Patents by Inventor Yoshiyuki Harada

Yoshiyuki Harada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130087761
    Abstract: According to one embodiment, a semiconductor light emitting device includes n-type and p-type semiconductor layers containing a nitride semiconductor and a light emitting layer. The emitting layer includes a barrier layer containing III group elements, and a well layer stacked with the barrier layer and containing III group elements. The barrier layer is divided into a first portion on an n-type semiconductor layer side and a second portion on a p-type semiconductor layer side, an In composition ratio in the III group elements of the second portion is lower than that of the first portion. The well layer is divided into a third portion on an n-type semiconductor layer side and a fourth portion on a p-type semiconductor layer side, an In composition ratio in the III group elements of the fourth portion is higher than that of the third portion.
    Type: Application
    Filed: February 27, 2012
    Publication date: April 11, 2013
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeya KIMURA, Yoshiyuki Harada, Hajime Nago, Koichi Tachibana, Shinya Nunoue
  • Patent number: 8399896
    Abstract: According to one embodiment, a semiconductor light emitting device includes n-type and p-type semiconductor layers, barrier layers, and a well layer. The n-type and p-type semiconductor layers and the barrier layers include nitride semiconductor. The barrier layers are provided between the n-type and p-type semiconductor layers. The well layer is provided between the barrier layers, has a smaller band gap energy than the barrier layers, and includes InGaN. At least one of the barrier layers includes first, second, and third layers. The second layer is provided closer to the p-type semiconductor layer than the first layer. The third layer is provided closer to the p-type semiconductor layer than the second layer. The second layer includes AlxGa1?xN (0<x?0.05). A band gap energy of the second layer is larger than the first and third layers. A total thickness of the first and second layers is not larger than the third layer.
    Type: Grant
    Filed: September 3, 2010
    Date of Patent: March 19, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Hikosaka, Tomonari Shioda, Yoshiyuki Harada, Shinya Nunoue
  • Publication number: 20130036759
    Abstract: A power module is attached to a refrigerant cooler in contact with the refrigerant cooler, and cooling is performed by dissipating heat to the refrigerant flowing in the refrigerant cooler. A controller outputs a driving signal to a drive circuit to reduce the number of switching operations of switching elements.
    Type: Application
    Filed: April 28, 2011
    Publication date: February 14, 2013
    Applicant: DAIKIN INDUSTRIES, LTD.
    Inventors: Yoshiyuki Harada, Toshiyuki Maeda
  • Publication number: 20120307303
    Abstract: A printing apparatus for conducting direct printing from a client computer via a web browser, having a storage unit 13 and 16 stores print setting information and a URL associated with the print setting information, and a job control unit 12 reads from the storage unit the print setting information associated with the URL entered by a user into the web browser, in order to reflect the print setting information as print setting of print data.
    Type: Application
    Filed: May 31, 2012
    Publication date: December 6, 2012
    Applicant: KONICA MINOLTA BUSINESS TECHNOLOGIES, INC.
    Inventor: Yoshiyuki HARADA
  • Publication number: 20120299015
    Abstract: According to one embodiment, a nitride semiconductor device includes a substrate and a semiconductor functional layer. The substrate is a single crystal. The semiconductor functional layer is provided on a major surface of the substrate and includes a nitride semiconductor. The substrate includes a plurality of structural bodies disposed in the major surface. Each of the plurality of structural bodies is a protrusion provided on the major surface or a recess provided on the major surface. An absolute value of an angle between a nearest direction of an arrangement of the plurality of structural bodies and a nearest direction of a crystal lattice of the substrate in a plane parallel to the major surface is not less than 1 degree and not more than 10 degrees.
    Type: Application
    Filed: February 27, 2012
    Publication date: November 29, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi TACHIBANA, Hisashi Yoshida, Hiroshi Ono, Hajime Nago, Yoshiyuki Harada, Toshiki Hikosaka, Maki Sugai, Toshiyuki Oka, Shinya Nunoue
  • Publication number: 20120299014
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type and having a major surface, a second semiconductor layer of a second conductivity type, and a light emitting layer provided between the first and second semiconductor layers. The major surface is opposite to the light emitting layer. The first semiconductor layer has structural bodies provided in the major surface. The structural bodies are recess or protrusion. A centroid of a first structural body aligns with a centroid of a second structural body nearest the first structural. hb, rb, and Rb satisfy rb/(2·hb)?0.7, and rb/Rb<1, where hb is a depth of the recess, rb is a width of a bottom portion of the recess, and Rb is a width of the protrusion.
    Type: Application
    Filed: February 24, 2012
    Publication date: November 29, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiki HIKOSAKA, Yoshiyuki Harada, Maki Sugai, Shinya Nunoue
  • Publication number: 20120298952
    Abstract: According to an embodiment, a semiconductor light emitting device includes a foundation layer, a first semiconductor layer, a light emitting layer, and a second semiconductor layer. The foundation layer has an unevenness having recesses, side portions, and protrusions. A first major surface of the foundation layer has an overlay-region. The foundation layer has a plurality of dislocations including first dislocations whose one ends reaching the recess and second dislocations whose one ends reaching the protrusion. A proportion of a number of the second dislocations reaching the first major surface to a number of all of the second dislocations is smaller than a proportion of a number of the first dislocations reaching the first major surface to a number of all of the first dislocations. A number of the dislocations reaching the overlay-region of the first major surface is smaller than a number of all of the first dislocations.
    Type: Application
    Filed: February 28, 2012
    Publication date: November 29, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiki HIKOSAKA, Yoshiyuki HARADA, Maki SUGAI, Shinya NUNOUE
  • Publication number: 20120138890
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer and a light emitting part. The light emitting part is provided between the n-type semiconductor layer and the p-type semiconductor layer and includes a first light emitting layer. The first light emitting layer includes a first barrier layer, a first well layer, a first n-side intermediate layer and a first p-side intermediate layer. The barrier layer, the well layer, the n-side layer and the p-side intermediate layer include a nitride semiconductor. An In composition ratio in the n-side layer decreases along a first direction from the n-type layer toward the p-type layer. An In composition ratio in the p-side layer decreases along the first direction. An average change rate of the In ratio in the p-side layer is lower than an average change rate of the In ratio in the n-side layer.
    Type: Application
    Filed: August 19, 2011
    Publication date: June 7, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomonari SHIODA, Toshiki Hikosaka, Yoshiyuki Harada, Naoharu Sugiyama, Shinya Nunoue
  • Publication number: 20120032209
    Abstract: According to one embodiment, a semiconductor light emitting device includes: semiconductor layers; a multilayered structural body; and a light emitting portion. The multilayered structural body is provided between the semiconductor layers, and includes a first layer and a second layer including In. The light emitting portion is in contact with the multilayered structural body between the multilayered structural body and p-type semiconductor layer, and includes barrier layers and a well layer including In with an In composition ratio among group III elements higher than an In composition ratio among group III elements in the second layer. An average lattice constant of the multilayered structural body is larger than that of the n-type semiconductor layer. Difference between the average lattice constant of the multilayered structural body and that of the light emitting portion is less than difference between that of the multilayered structural body and that of the n-type semiconductor layer.
    Type: Application
    Filed: February 23, 2011
    Publication date: February 9, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomonari SHIODA, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
  • Publication number: 20120012814
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting part provided therebetween. The light emitting part includes a plurality of light emitting layers. Each of the light emitting layers includes a well layer region and a non-well layer region which is juxtaposed with the well layer region in a plane perpendicular to a first direction from the n-type semiconductor layer towards the p-type semiconductor layer. Each of the well layer regions has a common An In composition ratio. Each of the well layer regions includes a portion having a width in a direction perpendicular to the first direction of 50 nanometers or more.
    Type: Application
    Filed: February 25, 2011
    Publication date: January 19, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki HARADA, Toshiki Hikosaka, Tomonari Shioda, Koichi Tachibana, Hajime Nago, Shinya Nunoue
  • Patent number: 8093083
    Abstract: In one embodiment, a method is disclosed for manufacturing a semiconductor light emitting device. The device includes a crystal layer including a nitride semiconductor. The crystal layer contains In and Ga atoms. The method can include forming the crystal layer by supplying a source gas including a first molecule including Ga atoms and a second molecule including In atoms onto a base body. The crystal layer has a ratio xs of a number of the In atoms to a total of the In atoms and the Ga atoms being not less than 0.2 and not more than 0.4. A vapor phase supply ratio xv of In is a ratio of a second partial pressure to a total of first and second partial pressures. The first and second partial pressures are pressure of the first and second molecules and degradation species of the first and second molecules on the source gas, respectively. (1?1/xv)/(1?1/xs) is less than 0.1.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: January 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Hikosaka, Tomonari Shioda, Yoshiyuki Harada, Naoharu Sugiyama, Koichi Tachibana, Shinya Nunoue
  • Publication number: 20110222149
    Abstract: According to the embodiments, an easy-to-fabricate light-emitting apparatus is provided in which a plurality of phosphors is disposed so as not to overlap each other. The light-emitting apparatus includes a light source that emits excitation light; a substrate having a protrusion and recess configuration where first planes and second planes which intersect the first planes are formed periodically; first phosphor layers formed on the first planes and absorbing the excitation light to emit a first fluorescence; and second phosphor layers formed on the second planes and absorbing the excitation light to emit a second fluorescence with a wavelength different from that of the first fluorescence.
    Type: Application
    Filed: September 2, 2010
    Publication date: September 15, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shinji SAITO, Yasushi Hattori, Yoshiyuki Harada, Shinya Nunoue
  • Publication number: 20110204394
    Abstract: According to one embodiment, a semiconductor light emitting device includes n-type and p-type semiconductor layers, barrier layers, and a well layer. The n-type and p-type semiconductor layers and the barrier layers include nitride semiconductor. The barrier layers are provided between the n-type and p-type semiconductor layers. The well layer is provided between the barrier layers, has a smaller band gap energy than the barrier layers, and includes InGaN. At least one of the barrier layers includes first, second, and third layers. The second layer is provided closer to the p-type semiconductor layer than the first layer. The third layer is provided closer to the p-type semiconductor layer than the second layer. The second layer includes AlxGa1?xN (0<x?0.05). A band gap energy of the second layer is larger than the first and third layers. A total thickness of the first and second layers is not larger than the third layer.
    Type: Application
    Filed: September 3, 2010
    Publication date: August 25, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiki HIKOSAKA, Tomonari Shioda, Yoshiyuki Harada, Shinya Nunoue
  • Publication number: 20110197808
    Abstract: Certain embodiments provide a crystal growth method for nitride semiconductors, including: growing a first semiconductor layer containing InxGa1-xN (0<x?1) on a substrate at a first growth temperature, with the use of a first carrier gas formed with an inert gas; growing a second semiconductor layer containing InyGa1-yN (0?y<1, y<x) on the first semiconductor layer at a second growth temperature higher than the first growth temperature, with the use of a second carrier gas containing the inert gas and H2 gas, an amount of the H2 gas being smaller than an amount of the inert gas; and growing a third semiconductor layer containing InzGa1-zN (0?z<1, z<x) on the second semiconductor layer at the second growth temperature, with the use of a third carrier gas containing the inert gas and H2 gas, an amount of the H2 gas in the third carrier gas being a smaller than the amount of H2 gas in the second carrier gas.
    Type: Application
    Filed: September 2, 2010
    Publication date: August 18, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomonari SHIODA, Toshiki Hikosaka, Yoshiyuki Harada, Koichi Tachibana, Shinya Nunoue
  • Patent number: 7985981
    Abstract: There is provided a semiconductor light-emitting device including a semiconductor light-emitting element, a phosphor layer disposed in a light path of a light emitted from the semiconductor light-emitting element, containing a phosphor to be excited by the light and having a cross-section in a region of a diameter which is 1 mm larger than that of a cross-section of the light path, and a heat-releasing member disposed in contact with at least a portion of the phosphor layer and exhibiting a higher thermal conductance than that of the phosphor layer.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: July 26, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Rei Hashimoto, Yasushi Hattori, Takahiro Sato, Jongil Hwang, Maki Sugai, Yoshiyuki Harada, Shinji Saito, Shinya Nunoue
  • Publication number: 20110143463
    Abstract: According to one embodiment, a vapor deposition method is disclosed for forming a nitride semiconductor layer on a substrate by supplying a group III source-material gas and a group V source-material gas. The method can deposit a first semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of not less than 10 atomic percent by supplying the group III source-material gas from a first outlet and by supplying the group V source-material gas from a second outlet. The method can deposit a second semiconductor layer including a nitride semiconductor having a compositional proportion of Al in group III elements of less than 10 atomic percent by mixing the group III and group V source-material gases and supplying the mixed group III and group V source-material gases from at least one of the first outlet and the second outlet.
    Type: Application
    Filed: September 3, 2010
    Publication date: June 16, 2011
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshiyuki HARADA, Koichi Tachibana, Toshiki Hikosaka, Hajime Nago, Shinya Nunoue
  • Publication number: 20110067625
    Abstract: A crystal growth method for forming a semiconductor film, the method includes: while revolving one or more substrates about a rotation axis, passing raw material gas and carrier gas from the rotation axis side in a direction substantially parallel to a major surface of the substrate. The center of the substrate is located on a side nearer to the rotation axis than a position at which growth rate of the semiconductor film formed by thermal decomposition of the raw material gas is maximized.
    Type: Application
    Filed: November 29, 2010
    Publication date: March 24, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masaaki Onomura, Yoshiyuki Harada
  • Patent number: 7862657
    Abstract: A crystal growth method for forming a semiconductor film, the method includes: while revolving one or more substrates about a rotation axis, passing raw material gas and carrier gas from the rotation axis side in a direction substantially parallel to a major surface of the substrate. The center of the substrate is located on a side nearer to the rotation axis than a position at which growth rate of the semiconductor film formed by thermal decomposition of the raw material gas is maximized.
    Type: Grant
    Filed: July 24, 2007
    Date of Patent: January 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaaki Onomura, Yoshiyuki Harada
  • Publication number: 20100187497
    Abstract: A semiconductor device includes an underlying layer, and a light emitting layer which is formed on the underlying layer and in which a barrier layer made of InAlGaN and a quantum well layer made of InGaN are alternately stacked.
    Type: Application
    Filed: March 3, 2010
    Publication date: July 29, 2010
    Inventors: Hajime NAGO, Koichi Tachibana, Shinji Saito, Yoshiyuki Harada, Shinya Nunoue
  • Publication number: 20100148203
    Abstract: There is provided a semiconductor light-emitting device including a semiconductor light-emitting element, a phosphor layer disposed in a light path of a light emitted from the semiconductor light-emitting element, containing a phosphor to be excited by the light and having a cross-section in a region of a diameter which is 1 mm larger than that of a cross-section of the light path, and a heat-releasing member disposed in contact with at least a portion of the phosphor layer and exhibiting a higher thermal conductance than that of the phosphor layer.
    Type: Application
    Filed: December 15, 2009
    Publication date: June 17, 2010
    Inventors: Rei HASHIMOTO, Yasushi Hattori, Takahiro Sato, Jongil Hwang, Maki Sugai, Yoshiyuki Harada, Shinji Saito, Shinya Nunoue