Patents by Inventor Yoshiyuki Ishigaki
Yoshiyuki Ishigaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6891743Abstract: A CMOS-SRAM has a plurality of full CMOS type memory cells (1) and a capacity plate (2). The memory cells (1) are two-dimensionally arranged in the row direction and in the column direction. The capacity plate 2 adds an additional capacity to nodes ND1 and ND2 for storing data in order to reduce soft errors. The capacity plate (2) is common with the plurality of memory cells (1). The capacity plates (2) are separated by every column, that is in the row direction. The capacity plate (2) is connected to a power voltage line VDD so as to simplify the voltage supplying system. When a stand-by failure occurs in the memory cell (1) of a certain column, the memory cell (1) is replaced with a redundant memory cell.Type: GrantFiled: July 16, 2002Date of Patent: May 10, 2005Assignee: Renesas Technology Corp.Inventors: Shigeki Ohbayashi, Yoshiyuki Ishigaki, Takahiro Yokoyama
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Publication number: 20050083756Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: ApplicationFiled: October 25, 2004Publication date: April 21, 2005Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Hidemoto Tomita, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Patent number: 6853022Abstract: A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.Type: GrantFiled: January 29, 2003Date of Patent: February 8, 2005Assignee: Renesas Technology Corp.Inventors: Tsuyoshi Koga, Yoshiyuki Ishigaki, Motoi Ashida, Yukio Maki, Yasuhiro Fujii, Tomohiro Hosokawa, Takashi Terada, Makoto Dei, Yasuichi Masuda
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Patent number: 6831852Abstract: A semiconductor device includes: a capacitor: an access transistor with impurity regions, controlling input/output of charge stored in the capacitor, one of the impurity regions being electrically connected to the capacitor; a latch circuit located above a silicon substrate, and storing the potential of a storage node of the capacitor; and a bit line connected to the other of the impurity regions of the access transistor T6. At least a portion of the latch circuit is formed above the bit line.Type: GrantFiled: May 22, 2003Date of Patent: December 14, 2004Assignee: Renesas Technology Corp.Inventors: Yoshiyuki Ishigaki, Tsuyoshi Koga, Yasuhiro Fujii
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Patent number: 6812534Abstract: An SRAM comprises a memory cell including first and second access nMOS transistors, first and second driver nMOS transistors and first and second load pMOS transistors, polysilicon wires forming gates of the first and second access nMOS transistors and polysilicon wires extending in the same direction as the polysilicon wires for forming gates of the first and second driver nMOS transistors and gates of the first and second load pMOS transistors. The gate widths of the first and second access nMOS transistors and those of the first and second driver nMOS transistors are equalized with each other.Type: GrantFiled: February 13, 2003Date of Patent: November 2, 2004Assignee: Renesas Technology Corp.Inventors: Yoshiyuki Ishigaki, Tomohiro Hosokawa, Yukio Maki
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Patent number: 6812574Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: GrantFiled: July 9, 2002Date of Patent: November 2, 2004Assignee: Renesas Technology Corp.Inventors: Hidemoto Tomita, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Patent number: 6781869Abstract: A semiconductor memory having: a full CMOS-type of memory cell (10) including an n-type bulk access transistor (7, 8), an n-type bulk driver transistor (5, 6) and a p-type bulk load transistor (3, 4) by twos, and a charge capacitance adding charge capacitor element (9) connected to cell nodes (N1, N2) in order to secure a soft error resistance. In the semiconductor memory, an insulating film (14) and a conductive film (15) are directly formed on each upper side of first and second cell nodes (N1, N2) for constituting a charge capacitor element (9) for adding a charge capacitance. The insulating film (14) is held between the cell node (N1, N2) and the conductive film (15), covering both first and second cell nodes (N1, N2) in common.Type: GrantFiled: December 26, 2002Date of Patent: August 24, 2004Assignee: Renesas Technology Corp.Inventors: Shigeki Ohbayashi, Yoshiyuki Ishigaki, Takahiro Yokoyama
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Patent number: 6774441Abstract: A semiconductor device according to the present invention includes a silicon substrate having a main surface, a gate electrode provided on the main surface of the silicon substrate, a first sidewall insulating film provided to cover a side surface of the gate electrode and including two layers of an oxide sidewall film as an underlay and a nitride sidewall film, a second sidewall insulating film provided to cover a surface of the first sidewall insulating film, and a cobalt silicide layer arranged above source and drain regions and at a position farther than the second sidewall insulating film from the gate electrode. The second sidewall insulating film fills in a removed portion located at a lower end of the oxide sidewall film. This allows a semiconductor device formed by employing a salicide process to prevent increase of leak current caused by a metal silicide layer.Type: GrantFiled: January 13, 2003Date of Patent: August 10, 2004Assignee: Renesas Technology Corp.Inventors: Yukio Maki, Yoshiyuki Ishigaki, Yasuhiro Fujii
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Publication number: 20040150019Abstract: A semiconductor memory device includes a memory cell, and first and second capacitive elements. The memory cell has a pair of inverters each including first and second driver nMOS transistors and first and second TFTs, and first and second access nMOS transistors. The first and second capacitive elements is connected to the drain of first and second access nMOS transistors, the drain of first and second driver nMOS transistors, and the drain of first and second TFTs. The gate width of first and second driver nMOS transistors is set at least 1.2 times longer than the gate width of first and second access nMOS transistors.Type: ApplicationFiled: July 25, 2003Publication date: August 5, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yasushi Nakashima, Takashi Izutsu, Yoshiyuki Ishigaki
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Publication number: 20040120179Abstract: A semiconductor device includes: a capacitor: an access transistor with impurity regions, controlling input/output of charge stored in the capacitor, one of the impurity regions being electrically connected to the capacitor; a latch circuit located above a silicon substrate, and storing the potential of a storage node of the capacitor; and a bit line connected to the other of the impurity regions of the access transistor T6. At least a portion of the latch circuit is formed above the bit line.Type: ApplicationFiled: May 22, 2003Publication date: June 24, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yoshiyuki Ishigaki, Tsuyoshi Koga, Yasuhiro Fujii
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Publication number: 20040046214Abstract: An SRAM comprises a memory cell including first and second access nMOS transistors, first and second driver nMOS transistors and first and second load pMOS transistors, polysilicon wires forming gates of the first and second access nMOS transistors and polysilicon wires extending in the same direction as the polysilicon wires for forming gates of the first and second driver nMOS transistors and gates of the first and second load pMOS transistors. The gate widths of the first and second access nMOS transistors and those of the first and second driver nMOS transistors are equalized with each other.Type: ApplicationFiled: February 13, 2003Publication date: March 11, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yoshiyuki Ishigaki, Tomohiro Hosokawa, Yukio Maki
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Publication number: 20040032764Abstract: A semiconductor memory device having as its main storage portion a capacitor storing charges as binary information and an access transistor controlling input/output of the charges to/from the capacitor, and eliminating the need for refresh, is obtained. The semiconductor memory device includes a capacitor with a storage node located above a semiconductor substrate and holding the charges corresponding to a logical level of stored binary information, an access transistor located on the semiconductor substrate surface and controlling input/output of the charges accumulated in the capacitor, and a latch circuit located on the semiconductor substrate and maintaining a potential of the capacitor storage node. At least one of circuit elements constituting the latch circuit is located above the access transistor.Type: ApplicationFiled: January 29, 2003Publication date: February 19, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Tsuyoshi Koga, Yoshiyuki Ishigaki, Motoi Ashida, Yukio Maki, Yasuhiro Fujii, Tomohiro Hosokawa, Takashi Terada, Makoto Dei, Yasuichi Masuda
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Publication number: 20040026747Abstract: A semiconductor device according to the present invention includes a silicon substrate having a main surface, a gate electrode provided on the main surface of the silicon substrate, a first sidewall insulating film provided to cover a side surface of the gate electrode and including two layers of an oxide sidewall film as an underlay and a nitride sidewall film, a second sidewall insulating film provided to cover a surface of the first sidewall insulating film, and a cobalt silicide layer arranged above source and drain regions and at a position farther than the second sidewall insulating film from the gate electrode. The second sidewall insulating film fills in a removed portion located at a lower end of the oxide sidewall film. This allows a semiconductor device formed by employing a salicide process to prevent increase of leak current caused by a metal silicide layer.Type: ApplicationFiled: January 13, 2003Publication date: February 12, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yukio Maki, Yoshiyuki Ishigaki, Yasuhiro Fujii
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Patent number: 6632716Abstract: A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a gate insulating film on the element forming region and extended over the element isolating film; first and second impurity regions formed in the element forming region, whose portions exposed from a surface of the semiconductor substrate are made in contact with the element isolating film and are located opposite to each other under the gate electrode; a first insulating film formed near the gate electrode on the first impurity region, and extended over the gate electrode and near an extended portion of the gate electrode within the element isolating film; and a second insulating film formed near the gate electrode on the second impurity region.Type: GrantFiled: February 8, 2001Date of Patent: October 14, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Yoshiyuki Ishigaki
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Publication number: 20030142538Abstract: A semiconductor memory having: a full CMOS-type of memory cell (10) including an n-type bulk access transistor (7, 8), an n-type bulk driver transistor (5, 6) and a p-type bulk load transistor (3, 4) by twos, and a charge capacitance adding charge capacitor element (9) connected to cell nodes (N1, N2) in order to secure a soft error resistance. In the semiconductor memory, an insulating film (14) and a conductive film (15) are directly formed on each upper side of first and second cell nodes (N1, N2) for constituting a charge capacitor element (9) for adding a charge capacitance. The insulating film (14) is held between the cell node (N1, N2) and the conductive film (15), covering both first and second cell nodes (N1, N2) in common.Type: ApplicationFiled: December 26, 2002Publication date: July 31, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Shigeki Ohbayashi, Yoshiyuki Ishigaki, Takahiro Yokoyama
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Publication number: 20030133335Abstract: A CMOS-SRAM has a plurality of full CMOS type memory cells (1) and a capacity plate (2). The memory cells (1) are two-dimensionally arranged in the row direction and in the column direction. The capacity plate 2 adds an additional capacity to nodes ND1 and ND2 for storing data in order to reduce soft errors. The capacity plate (2) is common with the plurality of memory cells (1). The capacity plates (2) are separated by every column, that is in the row direction. The capacity plate (2) is connected to a power voltage line VDD so as to simplify the voltage supplying system. When a stand-by failure occurs in the memory cell (1) of a certain column, the memory cell (1) is replaced with a redundant memory cell.Type: ApplicationFiled: July 16, 2002Publication date: July 17, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Shigeki Ohbayashi, Yoshiyuki Ishigaki, Takahiro Yokoyama
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Publication number: 20030128565Abstract: A semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, a first gate wiring element 3a, 3b, a second gate wiring element 3c, 3d, a first connector 5a, 5b, and a second connector 5c, 5d. Each memory cell 10 has first and second sets having a driver transistor 11, a load transistor 12, and an access transistor 13. The word lines are arranged in parallel to each other along a first direction. The bit lines are arranged in parallel to each other along a second direction perpendicular to the first direction. The first gate wiring element comprises a gate electrode of the first driver transistor and the first load transistor, and has a rectangular shape having straight line on opposite sides. The second gate wiring element comprises a gate electrode of the access transistor and has a rectangular shape having straight line on opposite sides.Type: ApplicationFiled: July 9, 2002Publication date: July 10, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Hidemoto Tomita, Shigeki Ohbayashi, Yoshiyuki Ishigaki
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Patent number: 6404024Abstract: There is described a semiconductor device whose structure is suitable for controlling the threshold values for operation of transistors, as well as for inexpensive fabrication of transistors whose threshold values for operation assume small values. A field-oxide film is formed on a silicon substrate through use of an oxidation-resistance mask, by means of the local oxidation of silicon (LOCOS) method. On the silicon substrate, there is formed an access transistor whose source/drain region is to be formed in active regions and whose channel region is to be formed in another active region. A protuberance is formed in the field-oxide film so as to bulge toward the active region where the channel region is to be formed. A bird's beak, which would grow during the course of formation of the field-oxide film, encounters difficulty in growing in the protuberance, as a result of which a trench is formed in a boundary area between the protuberance and the active region where the channel region is to be formed.Type: GrantFiled: March 2, 2000Date of Patent: June 11, 2002Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Yoshiyuki Ishigaki
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Patent number: 6271569Abstract: According to a semiconductor device and a method of manufacturing the same, a storage node has an increased capacity, and a resistance against soft error is improved. A GND interconnection is formed on a first interconnection layer including storage node portions with a dielectric film therebetween. Thereby, the storage node portions, the dielectric film, and the GND interconnection form a capacity element of the storage node portion. The first interconnection layer is arranged symmetrically around the center of the memory cell, and a plurality of memory cells having the same layout and neighboring to each other are arranged along the word lines.Type: GrantFiled: January 16, 1998Date of Patent: August 7, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshiyuki Ishigaki, Hiroki Honda
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Patent number: 6268627Abstract: In an access transistor formed on a silicon substrate, its drain region is formed of n− type and n+ type drain regions and its source region is formed of n− type and n+ type source regions. In a driver transistor, its source region is formed of n− type and n++ type source regions and its drain regions is formed of n− type and n+ type drain regions. The n+ +type source region is formed deeper than the n+ type drain region. Accordingly, a semiconductor device ensuring improvement in a static noise margin while suppressing increase in manufacturing cost is provided.Type: GrantFiled: November 24, 1998Date of Patent: July 31, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yoshiyuki Ishigaki, Yasuhiro Fujii