Abstract: A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a gate insulating film on the element forming region and extended over the element isolating film; first and second impurity regions formed in the element forming region, whose portions exposed from a surface of the semiconductor substrate are made in contact with the element isolating film and are located opposite to each other under the gate electrode; a first insulating film formed near the gate electrode on the first impurity region, and extended over the gate electrode and near an extended portion of the gate electrode within the element isolating film; and a second insulating film formed near the gate electrode on the second impurity region.

Abstract: P+-type source/drain regions for load transistors and N+-type source/drain regions for driver transistors are connected by means of P+-type source/drain region outgoing lead and N+-type source/drain region outgoing lead via direct contact holes. The drain region outgoing lead for the load transistors and ground lead are formed in a three-dimensionally overlapping manner, and the drain region outgoing lead for the driver transistors connected to memory nodes on one side and the drain region outgoing lead for the load transistors connected to memory nodes on the other side are also formed in a three-dimensionally overlapping manner, whereby memory node charge accumulators are constituted.

Abstract: A semiconductor device including a shunt interconnection which operates at higher speed and permits high density integration is provided. In the semiconductor device including the shunt interconnection, a shunt connection region for a word line and a first shunt interconnection including a metal are formed in the memory cell region. In the memory cell region, shunt connection region and shunt interconnection are electrically connected with each other through a word line contact plug formed in a contact hole.

Abstract: A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a gate insulating film on the element forming region and extended over the element isolating film; first and second impurity regions formed in the element forming region, whose portions exposed from a surface of the semiconductor substrate are made in contact with the element isolating film and are located opposite to each other under the gate electrode; a first insulating film formed near the gate electrode on the first impurity region, and extended over the gate electrode and near an extended portion of the gate electrode within the element isolating film; and a second insulating film formed near the gate electrode on the second impurity region.

Abstract: An SRAM is provided with a high-resistance element for loading including a high-resistance portion, which extends onto adjacent memory cell. An interlayer insulating film is formed between the high-resistance portions.

Abstract: P.sup.+ -type source/drain regions for load transistors and N.sup.+ -type source/drain regions for driver transistors are connected by means of P.sup.+ -type source/drain region outgoing lead and N.sup.+ -type source/drain region outgoing lead via direct contact holes. The drain region outgoing lead for the load transistors and ground lead are formed in a three-dimensionally overlapping manner, and the drain region outgoing lead for the driver transistors connected to memory nodes on one side and the drain region outgoing lead for the load transistors connected to memory nodes on the other side are also formed in a three-dimensionally overlapping manner, whereby memory node charge accumulators are constituted.

Abstract: The present invention provides an improved static random access memory which can be manufactured into values as designed by photolithography. Second direct contract for connecting active region and ground line for first and second memory cells is provided at a boundary between the first memory cell and second memory cell. Second direct contact is divided into a plurality of portions.

Abstract: An internal voltage generating circuit down-converts an external supply voltage and changes a reduction in its output voltage level from the external supply voltage level as the external supply voltage increases. The internal supply voltage is kept lower than the external supply voltage by the constant value while the external supply voltage stays under a predetermined voltage. The reduction amount is increased in proportion to the external supply voltage while the external supply voltage is over the predetermined voltage.

Abstract: The present invention provides an improved static random access memory which can be manufactured into values as designed by photolithography. Second direct contract for connecting active region and ground line for first and second memory cells is provided at a boundary between the first memory cell and second memory cell. Second direct contact is divided into a plurality of portions.

Abstract: A groove is formed at a surface of a p.sup.- -well region. One of source/drain regions of each of access transistors has an n.sup.- -impurity region and an n.sup.+ -impurity region forming an LDD structure. Another n.sup.- -impurity region is disposed such that n.sup.+ -impurity region is located between these n.sup.- -impurity regions, and is formed at the whole bottom surface of groove. Thereby, it is possible to provide a semiconductor memory device of a high performance including an SRAM in which resistance against soft error is improved, a junction leak current is reduced and a current consumption during standby can be reduced.

Abstract: The earth wire is a conductive lead located at the nearest position to a flat surface of the semiconductor substrate, and the earth wire and the word lines are arranged so that these are not formed on the other wires in the memory cell, the wiring resistance is reduced by shortening the wiring length, and there is little unevenness in the underlayer of the earth wire, whereby the read-out operation is stabilized. Furthermore, the earth wire is formed of a wiring layer which is near to the semiconductor substrate, so that the distance between the earth wire and a load element is set to be larger than that in the prior art. Therefore, it can be prevented that the earth wire acts as the gate electrode of a parasitic transistor and thus malfunction occurs. In addition, the shape of the field pattern can be simplified.

Abstract: The present invention is provided in order to suppress a leak current at an emitter-base junction and to implement a high-speed operation of a bipolar transistor. An n.sup.+ buried layer is formed at a surface of a p.sup.- silicon substrate. An n.sup.- epitaxial growth layer and an n.sup.+ diffused layer are formed on n.sup.+ buried layer. A p.sup.+ external base region and a p.sup.- base region are formed at a surface of n.sup.- epitaxial growth layer so as to be adjacent to each other. A first interlayer insulating layer having an opening is formed on p.sup.- base region. A groove which is located under opening and extends under first interlayer insulating layer is formed at a surface of p.sup.- base region. An n.sup.+ emitter region is formed at a bottom surface of groove within p.sup.- base region. A sidewall insulating layer is formed so as to expose n.sup.+ emitter region and to cover a sidewall of opening and to come into contact with a bottom surface of first interlayer insulating layer.

Abstract: The present invention provides an improved static random access memory which can be manufactured into values as designed by photolithography. Second direct contract for connecting active region and ground line for first and second memory cells is provided at a boundary between the first memory cell and second memory cell. Second direct contact is divided into a plurality of portions.

Abstract: A stable action of a memory cell in low voltage operation is realized, while assuring the reliability of the memory cell fined in structure for enhancing the degree of integration. An external supply voltage (V.sub.cc) is stepped down by a step-down transistor (Q1), and the stepped-down voltage is obtained as a potential for a bit line BIT. The external supply voltage (V.sub.cc) is also stepped down by a step-down transistor (Q5), and the stepped-down voltage is obtained as a potential for a bit line BIT. Furthermore, the external supply voltage (V.sub.cc) is stepped down by a step-down transistor (Q3), and the stepped-down voltage is obtained as an internal supply voltage for a memory cell (MC). On the contrary, to gate electrodes of both access transistors A1, A2, the external supply voltage V.sub.cc is directly applied through word drivers 1, 2, respectively.

Abstract: On an epitaxial layer (4) serving as a collector layer are formed an emitter layer (10), an intrinsic base layer (9) surrounding the emitter layer (10) while permitting the surface of the emitter layer (10) to be exposed, external base layers (8) and link base layers (7) lying between the intrinsic base layer (9) and external base layers (8). The intrinsic base layer between the emitter layer and the epitaxial layer serving as the collector layer has a relatively high impurity concentration, so that a collector-emitter breakdown voltage is not decreased. The link base layers between the intrinsic base layer and external base layers has a relatively low impurity concentration to suppress decrease in emitter-base junction breakdown voltage.

Abstract: An n.sup.+ buried layer is formed on a surface of p.sup.- semiconductor substrate. An n.sup.- epitaxial growth layer and an n.sup.+ diffusion layer are formed on a surface of n.sup.+ buried layer. A p.sup.- base region and p.sup.+ external base region adjoining to each other are formed on a surface of n.sup.- epitaxial growth layer. An an n.sup.+ emitter region is formed at a surface of p.sup.- base region. An emitter electrode is formed adjacently to n.sup.+ emitter region. The emitter electrode is made of polycrystalline silicon doped with phosphorus at a concentration from 1.times.10.sup.20 cm.sup.-3 to 6.times.10.sup.20 cm.sup.-3.

Abstract: Insulator films (5) formed on an epitaxial layer (3) are opened such that external base regions (17) are not covered with the insulator films (5). Cross sections (14a) of the insulator films (5) are concavely sloped downward from the insulator films (5) toward an intrinsic base region (18) in the vicinity of the epitaxial layer (3). Base electrodes (15) which are in contact with the insulator films (5) along the cross sections (14a) are connected to the external base regions (17), so that coverage of the base electrodes (15) over the external base regions (17) is improved. The base resistance of a bipolar transistor (101) is reduced.

Abstract: An n.sup.- epitaxial layer 4 is formed on the top face of a p type semiconductor substrate 1. A p.sup.+ buried layer 20 is formed by implanting ions in the region extending over the p type semiconductor substrate 1 and the n.sup.- epitaxial layer 4. A p.sup.+ channel stop is formed in the upper layer of the p.sup.+ buried layer 20 by ion implantation. A p well is formed extending from the upper layer of the p.sup.+ channel stop to the top face of the n.sup.- epitaxial layer. An n channel MOS type field effect transistor 200 is formed in the p well 22. It is possible to reliably isolate an element from an adjacent element thereto because of the structure.

Abstract: There is disclosed a C-BiCMOS semiconductor device in which a base electrode (300) of an NPN bipolar transistor and a drain electrode (360) of a PMOS transistor are formed of the same polycrystalline semiconductor, in which a base electrode (310) of a PNP bipolar transistor and a drain electrode (350) of an NMOS transistor are formed of the same polycrystalline semiconductor, and in which a source electrode (530) of the PMOS transistor and a source electrode (520) of the NMOS transistor are formed of aluminium wiring. The C-BiCMOS semiconductor device achieves preferable electric conductivity in the source electrodes, size reduction in the drain electrodes, and simplified process steps in the formation of the base electrodes of the bipolar transistors, so that the size of the devices is reduced in simple process steps without deterioration of the electric conductivity.

Abstract: The impurity concentration of an n.sup.+ buried layer 51a in the region for forming a p channel MOS transistor 23 is higher than the impurity concentration of an n.sup.+ buried layer 3a in the region for forming an npn bipolar transistor 21. N.sup.+ buried layers 3a and 51a are formed on a p type silicon substrate 1. An n.sup.- well region 10 is formed as a region for forming npn bipolar transistor 21 on n.sup.+ buried layer 3a. An n well region 12 is formed as a region for forming p channel MOS transistor 23 on n.sup.+ buried layer 51a. While the performance of npn bipolar transistor 21 is maintained, the performance of a CMOS transistor formed of an n channel MOS transistor 22 and p channel MOS transistor 23 is improved. In a Bi-CMOS semiconductor device, the performance of a bipolar transistor portion is maintained, while preventing the formation of a punch through and improving the latch up tolerance of a CMOS transistor portion.