Patents by Inventor Yoshiyuki Kurokawa

Yoshiyuki Kurokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11330213
    Abstract: An imaging device with low power consumption is provided. It includes a pixel capable of outputting difference data between two different frames, a circuit determining the significance of the difference data, a circuit controlling power supply, an A/D converter, and the like; obtains image data and then obtains difference data; and shuts off power supply to the A/D converter and the like in the case where it is determined that there is no difference, and continues or restarts the power supply to the A/D converter and the like when it is determined that there is a difference. Determining the significance of the difference data can be performed row by row in a pixel array or at nearly the same time in all the pixels included in the pixel array.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: May 10, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takashi Nakagawa, Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda
  • Patent number: 11314484
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: April 26, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Munehiro Kozuma, Takeshi Aoki, Seiichi Yoneda, Yoshiyuki Kurokawa
  • Publication number: 20220124275
    Abstract: A driving method of a semiconductor device that takes three-dimensional images with short duration is provided. In a first step, a light source starts to emit light, and first potential corresponding to the total amount of light received by a first photoelectric conversion element and a second photoelectric conversion element is written to a first charge accumulation region. In a second step, the light source stops emitting light and second potential corresponding to the total amount of light received by the first photoelectric conversion element and the second photoelectric conversion element is written to a second charge accumulation region. In a third step, first data corresponding to the potential written to the first charge accumulation region is read. In a fourth step, second data corresponding to the potential written to the second charge accumulation region is read.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 21, 2022
    Inventor: Yoshiyuki KUROKAWA
  • Patent number: 11281285
    Abstract: A method for controlling power supply in a semiconductor device including a CPU and a PLD which can hold data even in an off state is provided. The semiconductor device includes a processor, a programmable logic device, and a state control circuit. The programmable logic device includes a first nonvolatile memory circuit and has a function of holding data obtained by arithmetic processing of the programmable logic device when it is turned off. The state control circuit obtains data on the amount of a task performed by the programmable logic device in accordance with an operation of the processor. The programmable logic device detects the state of progress of the task and outputs a signal to the state control circuit. The state control circuit monitors the amount of the task and the state of progress of the task and turns off the programmable logic device when the task is completed.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 22, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Okamoto, Yoshiyuki Kurokawa
  • Publication number: 20220077205
    Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.
    Type: Application
    Filed: November 3, 2021
    Publication date: March 10, 2022
    Inventors: Yuki OKAMOTO, Yoshiyuki KUROKAWA, Hiroki INOUE, Takuro OHMARU
  • Patent number: 11264973
    Abstract: A semiconductor device capable of performing product-sum operation with low power consumption. The semiconductor device includes first and second logic circuits, first to fourth transistors, and first and second holding units. A low power supply potential input terminal of the first logic circuit is electrically connected to the first and third transistors. A low power supply potential input terminal of the second logic circuit is electrically connected to the second and fourth transistors. The potentials of second gates of the first and fourth transistors are held in the first holding unit as potentials corresponding to first data. The potentials of second gates of the second and third transistors are held in the second holding unit. The on/off states of the first to fourth transistors are determined by second data. A difference in signal input/output time between the first and second logic circuits depends on the first data and the second data.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: March 1, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hajime Kimura, Yoshiyuki Kurokawa
  • Patent number: 11264415
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: March 1, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura
  • Publication number: 20220045125
    Abstract: A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits; the first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits each have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When a potential corresponding to second data is input to each of the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring and the second circuit outputs a current to the other of the first wiring and the second wiring.
    Type: Application
    Filed: October 7, 2019
    Publication date: February 10, 2022
    Inventors: Hajime KIMURA, Yoshiyuki KUROKAWA
  • Patent number: 11239268
    Abstract: An object is to provide a pixel structure of a display device including a photosensor which prevents changes in an output of the photosensor and a decrease in imaging quality. The display device has a pixel layout structure in which a shielding wire is disposed between an FD and an imaging signal line (a PR line, a TX line, or an SE line) or between the FD and an image-display signal line in order to reduce or eliminate parasitic capacitance between the FD and a signal line for the purpose of suppressing changes in the potential of the FD. An imaging power supply line, image-display power supply line, a GND line, a common line, or the like whose potential is fixed, such as a common potential line, is used as a shielding wire.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: February 1, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Aoki, Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura
  • Patent number: 11232831
    Abstract: A semiconductor device including cells arranged in a matrix with m rows and n columns, where each of m and n is an integer of 2 or more, in which the cells retain first data with m rows and n columns, the cells input second data with m rows, and the semiconductor device outputs third data with m rows obtained by vector-matrix multiplication of the first data and the second data, is provided.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: January 25, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Publication number: 20220020793
    Abstract: In a CMOS image sensor in which a plurality of pixels is arranged in a matrix, a transistor in which a channel formation region includes an oxide semiconductor is used for each of a charge accumulation control transistor and a reset transistor which are in a pixel portion. After a reset operation of the signal charge accumulation portion is performed in all the pixels arranged in the matrix, a charge accumulation operation by the photodiode is performed in all the pixels, and a read operation of a signal from the pixel is performed per row. Accordingly, an image can be taken without a distortion.
    Type: Application
    Filed: September 30, 2021
    Publication date: January 20, 2022
    Inventors: Yoshiyuki KUROKAWA, Takayuki IKEDA, Hikaru TAMURA, Munehiro KOZUMA, Masataka IKEDA, Takeshi AOKI
  • Patent number: 11227543
    Abstract: An electronic device capable of efficiently recognizing a handwritten character is provided. The electronic device includes a first circuit, a display portion, and a touch sensor. The first circuit includes a neural network. The display portion includes a flexible display. The touch sensor has the function of outputting an input handwritten character as image information to the first circuit. The first circuit has the function of analyzing the image information and converting the image information into character information, and a function of displaying an image including the character information on the display portion. The analysis is performed by inference through the use of the neural network.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: January 18, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shintaro Harada, Yoshiyuki Kurokawa, Takeshi Aoki, Yuki Okamoto, Hiroki Inoue, Koji Kusunoki, Yosuke Tsukamoto, Katsuki Yanagawa, Kei Takahashi, Shunpei Yamazaki
  • Patent number: 11223789
    Abstract: A driving method of a semiconductor device that takes three-dimensional images with short duration is provided. In a first step, a light source starts to emit light, and first potential corresponding to the total amount of light received by a first photoelectric conversion element and a second photoelectric conversion element is written to a first charge accumulation region. In a second step, the light source stops emitting light and second potential corresponding to the total amount of light received by the first photoelectric conversion element and the second photoelectric conversion element is written to a second charge accumulation region. In a third step, first data corresponding to the potential written to the first charge accumulation region is read. In a fourth step, second data corresponding to the potential written to the second charge accumulation region is read.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: January 11, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 11205669
    Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: December 21, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Okamoto, Yoshiyuki Kurokawa, Hiroki Inoue, Takuro Ohmaru
  • Patent number: 11202026
    Abstract: A semiconductor device with an arithmetic processing function is provided. In the semiconductor device, an imaging portion and an arithmetic portion are electrically connected to each other through an analog processing circuit. The imaging portion includes a pixel array in which pixels used for imaging and reference pixels used for image processing are arranged in a matrix, and a row decoder. The arithmetic portion includes a memory element array in which memory elements and reference memory elements are arranged in a matrix, an analog processing circuit, a row decoder, and a column decoder.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: December 14, 2021
    Inventor: Yoshiyuki Kurokawa
  • Publication number: 20210384193
    Abstract: A semiconductor device that can perform product-sum operation with low power consumption is provided. The semiconductor device includes first and second circuits. The first circuit includes a first holding node and the second circuit includes a second holding node. The first circuit is electrically connected to first and second input wirings and first and second wirings, the second circuit is electrically connected to the first and second input wirings and the first and second wirings, and the first and second circuits have a function of holding first and second potentials corresponding to first data at the first and second holding nodes. When potentials corresponding to second data are input to the first and second input wirings, the first circuit outputs a current to one of the first wiring and the second wiring, and the second circuit outputs a current to the other of the first wiring and the second wiring.
    Type: Application
    Filed: October 28, 2019
    Publication date: December 9, 2021
    Inventors: Hajime KIMURA, Yoshiyuki KUROKAWA
  • Publication number: 20210384239
    Abstract: An imaging device capable of image processing is provided. The imaging device can retain analog data (image data) obtained by an image-capturing operation in a pixel and perform a product-sum operation of the analog data and a predetermined weight coefficient in the pixel to convert the data into binary data. When the binary data is taken in a neural network or the like, processing such as image recognition can be performed. Since enormous volumes of image data can be retained in pixels in the state of analog data, processing can be performed efficiently.
    Type: Application
    Filed: August 17, 2021
    Publication date: December 9, 2021
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Takayuki Ikeda, Yoshiyuki Kurokawa, Shintaro Harada, Hidetomo Kobayashi, Roh Yamamoto, Kiyotaka Kimura, Takashi Nakagawa, Yusuke Negoro
  • Patent number: 11189656
    Abstract: An object is to provide an imaging device in which a circuit for reading a signal is provided in a pixel region. The imaging device includes a first pixel and a second pixel. The first pixel is capable of outputting a first signal output from a pixel circuit included in the first pixel or a second signal input from the first pixel in the previous stage, to the first pixel or the second pixel in the next stage. The second pixel is capable of outputting, to the outside, the first signal or the second signal, which is input from the first pixel in the previous stage, or a third signal output from a pixel circuit included in the second pixel.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: November 30, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Publication number: 20210358530
    Abstract: The operation speed of a semiconductor device is improved. The semiconductor device includes a first memory region and a second memory region; in the semiconductor device, a first memory cell in the first memory region is superior to a second memory cell in the second memory region in data retention characteristics such as a large storage capacitance or a large channel length-channel width ratio (L/W) of a transistor. When the semiconductor device is used as a cache memory or a main memory device of a processor, the first memory region mainly stores a start-up routine and is not used as a work region for arithmetic operation, and the second memory region is used as a work region for arithmetic operation. The first memory region becomes an accessible region when the processor is booted, and the first memory region becomes an inaccessible region when the processor is in normal operation.
    Type: Application
    Filed: July 22, 2021
    Publication date: November 18, 2021
    Inventors: Yoshiyuki KUROKAWA, Shunpei YAMAZAKI
  • Patent number: 11177299
    Abstract: A solid-state imaging device with high productivity and improved dynamic range is provided. In the imaging device including a photoelectric conversion element having an i-type semiconductor layer, functional elements, and a wiring, an area where the functional elements and the wiring overlap with the i-type semiconductor in a plane view is preferably less than or equal to 35%, further preferably less than or equal to 15%, and still further preferably less than or equal to 10% of the area of the i-type semiconductor in a plane view. Plural photoelectric conversion elements are provided in the same semiconductor layer, whereby a process for separating the respective photoelectric conversion elements can be reduced. The respective i-type semiconductor layers in the plural photoelectric conversion elements are separated by a p-type semiconductor layer or an n-type semiconductor layer.
    Type: Grant
    Filed: May 27, 2015
    Date of Patent: November 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuki Okamoto, Yoshiyuki Kurokawa, Hiroki Inoue, Takuro Ohmaru