Patents by Inventor Yoshiyuki Kurokawa

Yoshiyuki Kurokawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10885877
    Abstract: A novel semiconductor device or display system is provided. The display system includes a correction circuit having a function of correcting an image signal by utilizing artificial intelligence. Specifically, learning by an artificial neural network enables the correction circuit to correct an image signal so as to alleviate the image discontinuity. Then, by making an inference (recognition) utilizing the artificial neural network which has finished the learning, the image signal is corrected and compensation for the image discontinuity can be made. In this manner, the junction can be inconspicuous on the displayed image, improving the quality of a high-resolution image.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: January 5, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Publication number: 20200403016
    Abstract: A highly sensitive imaging device that can perform imaging even under a low illuminance condition is provided. One electrode of a photoelectric conversion element is electrically connected to one of a source electrode and a drain electrode of a first transistor and one of a source electrode and a drain electrode of a third transistor. The other of the source electrode and the drain electrode of the first transistor is electrically connected to a gate electrode of the second transistor. The other electrode of the photoelectric conversion element is electrically connected to a first wiring. A gate electrode of the first transistor is electrically connected to a second wiring. When a potential supplied to the first wiring is HVDD, the highest value of a potential supplied to the second wiring is lower than HVDD.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 24, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yoshiyuki KUROKAWA
  • Patent number: 10867240
    Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: December 15, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Publication number: 20200382730
    Abstract: An imaging device with reduced power consumption is provided. The imaging device includes an imaging portion and an encoder. First image data obtained by the imaging portion is transmitted to the encoder. The encoder includes a first circuit that forms a neural network, and the first circuit conducts feature extraction by the neural network on a first image to generate second image data. Note that since the first circuit has a function of performing convolution processing using a weight filter, the encoder can perform computation with a convolutional neural network.
    Type: Application
    Filed: April 20, 2018
    Publication date: December 3, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiyuki KUROKAWA, Tatsunori INOUE
  • Publication number: 20200349423
    Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.
    Type: Application
    Filed: July 21, 2020
    Publication date: November 5, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yoshiyuki KUROKAWA
  • Publication number: 20200349898
    Abstract: A display device that performs image correction in accordance with external light environment is provided. The display device includes a host device and an optical sensor. In addition, the display device includes a processing circuit. The host device has a function of performing arithmetic processing using a neural network on software and a function of performing supervised learning with the neural network. The processing circuit has a function of performing arithmetic processing using a neural network on hardware. The optical sensor has a function of obtaining illuminance of external light. The obtained illuminance of external light is inputted to the host device, and a luminance and color tone preferred by users are regarded as teacher data, whereby learning is performed on the neural network of the host device. A weight coefficient obtained through the learning is used as a weight coefficient of the neural network of the processing circuit.
    Type: Application
    Filed: July 17, 2020
    Publication date: November 5, 2020
    Inventor: Yoshiyuki KUROKAWA
  • Publication number: 20200342825
    Abstract: A novel semiconductor device is provided. The semiconductor device has a function of changing a pixel selection period in accordance with a distance from a driver circuit. Specifically, when the distance between a first pixel and the driver circuit is longer than the distance between a second pixel and the driver circuit, the pulse width of a selection signal supplied to the first pixel is set larger than the pulse width of a selection signal supplied to the second pixel. Accordingly, writing of image signals to pixels provided far from the driver circuit can be accurately performed while the selection period for pixels provided near the driver circuit is kept short.
    Type: Application
    Filed: January 11, 2018
    Publication date: October 29, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yoshiyuki KUROKAWA
  • Publication number: 20200320924
    Abstract: An object is to provide a semiconductor device with low power consumption. The semiconductor device includes a controller, a register, and an image processing portion. The image processing portion has a function of taking image data from a frame memory and a parameter from the register and processing the image data by using the parameter. The frame memory has a function of retaining the image data while power supply is stopped. The register has a function of retaining the parameter while power supply is stopped. The controller controls power supply to the register, the frame memory, and the image processing portion. The register includes first and second scan chain registers. The first scan chain register stores a parameter related to a first display region. The second scan chain register stores a parameter related to a second display region. A parameter is changed by loading of data of the first or second scan chain register.
    Type: Application
    Filed: May 7, 2020
    Publication date: October 8, 2020
    Inventor: Yoshiyuki KUROKAWA
  • Patent number: 10797706
    Abstract: A programmable logic device including an asynchronous circuit is provided. The programmable logic device includes a lookup table, a first circuit, and a second circuit. The first circuit receives a first signal and a second signal. The second circuit sends a third signal. The first circuit sends a fourth signal and a fifth signal, when receiving the third signal. The fourth signal has the same logic as the first signal. The fifth signal has the same logic as the second signal. The lookup table sends a sixth signal and a seventh signal, when receiving the fourth signal and the fifth signal. The second circuit sends an eighth signal, when receiving the sixth signal and the seventh signal. The first circuit sends a ninth signal, when receiving the eighth signal. The lookup table includes a memory. The sixth signal and the seventh signal are generated from data stored in the memory.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: October 6, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Publication number: 20200312851
    Abstract: A semiconductor device with a large storage capacity per unit area is provided. The disclosed semiconductor device includes a plurality of gain-cell memory cells each stacked over a substrate. Axes of channel length directions of write transistors of memory cells correspond to each other, and are substantially perpendicular to the top surface of the substrate. The semiconductor device can retain multi-level data. The channel of read transistors is columnar silicon (embedded in a hole penetrating gates of the read transistors). The channel of write transistors is columnar metal oxide (embedded in a hole penetrating the gates of the read transistors and gates, or write word lines, of the write transistors). The columnar silicon faces the gate of the read transistor with an insulating film therebetween. The columnar metal oxide faces the write word line with an insulating film, which is obtained by oxidizing the write word line, therebetween, and is electrically connected to the gate of the read transistor.
    Type: Application
    Filed: June 11, 2020
    Publication date: October 1, 2020
    Inventors: Yasuhiko TAKEMURA, Yoshiyuki KUROKAWA
  • Publication number: 20200295006
    Abstract: To provide a semiconductor device that can reduce power consumption and retain data for a long time and a memory device including the semiconductor device. The semiconductor device includes a word line divider, a memory cell, a first wiring, and a second wiring. The word line divider is electrically connected to the first wiring and the second wiring. The memory cell includes a first transistor with a dual-gate structure. A first gate of the first transistor is electrically connected to the first wiring, and a second gate of the first transistor is electrically connected to the second wiring. The word line divider supplies a high-level potential or a low-level potential to the first wiring and supplies a predetermined potential to the second wiring, whereby a threshold voltage of the first transistor is changed. With such a configuration, a semiconductor device that can reduce power consumption and retain data for a long time is driven.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Fumika Akasawa, Hiroki INOUE, Takashi NAKAGAWA, Yoshiyuki KUROKAWA
  • Patent number: 10769520
    Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: September 8, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Publication number: 20200266761
    Abstract: An oscillator capable of quick startup is provided. A transistor is provided between an output terminal of a certain stage inverter and an input terminal of the following stage inverter included in the voltage controlled oscillator. With the use of the on resistance of the transistor, the oscillation frequency of the clock signal is controlled. While supply of the power supply voltage is stopped, a signal that is input to the input terminal of the inverter just before supply of the power supply voltage is stopped is stored by turning off the transistor. This operation makes it possible to immediately output a clock signal that has the same frequency as that before supply of the power supply voltage is stopped at the time when the power supply voltage is supplied again.
    Type: Application
    Filed: May 7, 2020
    Publication date: August 20, 2020
    Inventors: Yuki OKAMOTO, Yoshiyuki KUROKAWA
  • Patent number: 10748479
    Abstract: A novel semiconductor device or a novel display system is provided. A signal generation portion monitors display conditions and controls the potentials output from a power supply circuit, in accordance with the display conditions. Specifically, a controller changes the parameter stored in a memory device when display conditions change. Then, the power supply circuit generates the potentials with the use of the changed parameter. Accordingly, the voltage applied to a light-emitting element can be controlled in accordance with the display conditions, which reduces the power consumption in a display portion.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: August 18, 2020
    Assignee: Semiconductor Energy Laboratories Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 10733946
    Abstract: A display device that performs image correction in accordance with external light environment is provided. The display device includes a host device and an optical sensor. In addition, the display device includes a processing circuit. The host device has a function of performing arithmetic processing using a neural network on software and a function of performing supervised learning with the neural network. The processing circuit has a function of performing arithmetic processing using a neural network on hardware. The optical sensor has a function of obtaining illuminance of external light. The obtained illuminance of external light is inputted to the host device, and a luminance and color tone preferred by users are regarded as teacher data, whereby learning is performed on the neural network of the host device. A weight coefficient obtained through the learning is used as a weight coefficient of the neural network of the processing circuit.
    Type: Grant
    Filed: August 22, 2017
    Date of Patent: August 4, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Publication number: 20200234108
    Abstract: To provide a semiconductor device which can execute the product-sum operation. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. First analog data is stored in the first memory cell, and reference analog data is stored in the second memory cell. The first memory cell and the second memory cell supply a first current and a second current, respectively, when a reference potential is applied as a selection signal. The offset circuit has a function of supplying a third current corresponding to a differential current between the first current and the second current. In the semiconductor device, the first memory and the second memory supply a fourth current and a fifth current, respectively, when a potential corresponding to second analog data is applied as a selection signal.
    Type: Application
    Filed: March 23, 2020
    Publication date: July 23, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Yoshiyuki KUROKAWA
  • Publication number: 20200227465
    Abstract: A semiconductor device including pixels arranged in a matrix of n rows and m columns, in which the pixels in the m-th column are shielded from light, is provided.
    Type: Application
    Filed: March 18, 2020
    Publication date: July 16, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Patent number: 10699794
    Abstract: An electronic device applicable to an artificial neuron network. The electronic device includes a first circuit, a second circuit, and first to sixth wirings. The first circuit includes a first transistor, a second transistor, and a capacitor. The second circuit includes a third transistor. A gate of the third transistor is electrically connected to the third wiring. The capacitor capacitively couples the third wiring and the gate of the second transistor. The first circuit is capable of storing a weight as an analog value. The first transistor is typically an oxide semiconductor transistor.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: June 30, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takayuki Ikeda, Yoshiyuki Kurokawa
  • Publication number: 20200204755
    Abstract: A semiconductor device with an arithmetic processing function is provided. In the semiconductor device, an imaging portion and an arithmetic portion are electrically connected to each other through an analog processing circuit 24. The imaging portion includes a pixel array 21 in which pixels 20 used for imaging and reference pixels 22 used for image processing are arranged in a matrix, and a row decoder 25. The arithmetic portion includes a memory element array 31 in which memory elements 30 and reference memory elements 32 are arranged in a matrix, an analog processing circuit 34, a row decoder 35, and a column decoder 36.
    Type: Application
    Filed: February 27, 2020
    Publication date: June 25, 2020
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Yoshiyuki Kurokawa
  • Publication number: 20200201603
    Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a plurality of operation circuits that can switch different kinds of operation processing; a plurality of switch circuits that can switch a connection state between the operation circuits; and a controller. The operation circuit includes a first memory that stores data corresponding to a weight parameter used in the plurality of kinds of operation processing. The operation circuit executes a product-sum operation by switching weight data in accordance with a context. The switch circuit includes a second memory that stores data for switching a plurality of connection states in response to switching of a second context signal. The controller generates a second context signal on the basis of a first context signal. The amount of data stored in the second memory can be smaller than the amount of data stored in the first memory in the operation circuit.
    Type: Application
    Filed: May 7, 2018
    Publication date: June 25, 2020
    Inventors: Munehiro KOZUMA, Takeshi AOKI, Seiichi YONEDA, Yoshiyuki KUROKAWA