Patents by Inventor Yoshiyuki Nakao
Yoshiyuki Nakao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7507666Abstract: An insulating film having a concave portion is formed on a semiconductor substrate. The inner surface of the concave portion and the upper surface of the insulating film are covered with an auxiliary film made of Cu alloy containing a first metal element other than Cu. A conductive member containing Cu as a main composition is deposited on the auxiliary film, the conductive member being embedded in the concave portion. Heat treatment is performed in an atmosphere containing P compound, Si compound or B compound. With this method, a content of element other than Cu in the conductive member can be reduced and a resistivity can be lowered.Type: GrantFiled: December 6, 2005Date of Patent: March 24, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Yoshiyuki Nakao, Hideki Kitada, Nobuyuki Ohtsuka, Noriyoshi Shimizu
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Publication number: 20090042386Abstract: A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A conductive member is buried in the recess. A semiconductor device is provided whose interlayer insulating film can be worked easily even if it is made to have a low dielectric constant.Type: ApplicationFiled: September 26, 2008Publication date: February 12, 2009Applicant: FUJITSU LIMITEDInventors: Noriyoshi Shimizu, Yoshiyuki Nakao, Hiroki Kondo, Takashi Suzuki, Nobuyuki Nishikawa
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Publication number: 20080286960Abstract: (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.Type: ApplicationFiled: July 11, 2008Publication date: November 20, 2008Applicant: FUJITSU LIMITEDInventors: Noriyoshi Shimizu, Nobuyuki Ohtsuka, Hideki Kitada, Yoshiyuki Nakao
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Patent number: 7413977Abstract: A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. Then a first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. Then conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. Then the semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.Type: GrantFiled: December 28, 2005Date of Patent: August 19, 2008Assignee: Fujitsu LimitedInventors: Noriyoshi Shimizu, Nobuyuki Ohtsuka, Hideki Kitada, Yoshiyuki Nakao
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Publication number: 20080113506Abstract: A method for fabricating a semiconductor device has forming an opening defined by an inner wall surface in an insulation film, covering said inner wall surface with a Cu—Mn alloy layer, depositing a first Cu layer over said Cu—Mn alloy layer without exposing said Cu—Mn alloy layer to the air, depositing a second Cu layer over said first Cu layer and filling said opening with said second Cu layer, and forming a barrier layer over said inner wall surface as a result of a reaction between Mn in said Cu—Mn alloy layer and said insulation film.Type: ApplicationFiled: November 13, 2007Publication date: May 15, 2008Applicant: FUJITSU LIMITEDInventors: Nobuyuki OHTSUKA, Noriyoshi SHIMIZU, Yoshiyuki NAKAO
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Publication number: 20070252280Abstract: A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A conductive member is buried in the recess. A semiconductor device is provided whose interlayer insulating film can be worked easily even if it is made to have a low dielectric constant.Type: ApplicationFiled: July 6, 2007Publication date: November 1, 2007Applicant: FUJITSU LIMITEDInventors: Noriyoshi Shimizu, Yoshiyuki Nakao, Hiroki Kondo, Takashi Suzuki, Nobuyuki Nishikawa
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Patent number: 7256500Abstract: A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A conductive member is buried in the recess. A semiconductor device is provided whose interlayer insulating film can be worked easily even if it is made to have a low dielectric constant.Type: GrantFiled: February 28, 2006Date of Patent: August 14, 2007Assignee: Fujitsu LimitedInventors: Noriyuki Shimizu, Yoshiyuki Nakao, Hiroki Kondo, Takashi Suzuki, Nobuyuki Nishikawa
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Publication number: 20070173055Abstract: A method for fabricating a semiconductor device includes the steps of forming an opening defined by an inner wall surface in an insulation film, forming a Cu—Mn alloy layer in the opening, depositing a Cu layer on the Cu—Mn alloy layer and filling the opening with the Cu layer, and forming a barrier layer as a result of reaction between Mn atoms in the Cu—Mn alloy layer and the insulation film, wherein the step of forming the barrier layer is conducted by exposing the Cu layer to an ambient that forms a gaseous reaction product when reacted with Mn.Type: ApplicationFiled: January 18, 2007Publication date: July 26, 2007Applicant: FUJITSU LIMITEDInventors: Nobuyuki Ohtsuka, Noriyoshi Shimizu, Yoshiyuki Nakao, Hisaya Sakai
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Publication number: 20070045851Abstract: An interlayer insulating film having a concave portion is formed on a semiconductor substrate. A tight adhesion film is formed on the inner surface of the concave portion and the upper surface of the insulating film. The surface of the adhesion layer is covered with an auxiliary film made of Cu alloy containing a first metal element. A conductive member containing a second metal element other than the first metal element is embedded in the concave portion, and deposited on the auxiliary film. Heat treatment is performed to make atoms of the first metal element in the auxiliary film segregate on the inner surface of the concave portion. The adhesion layer contains an element for enhancing tight adhesion of the auxiliary film more than if the auxiliary film is deposited directly on a surface of the interlayer insulating film.Type: ApplicationFiled: November 30, 2005Publication date: March 1, 2007Applicant: FUJITSU LIMITEDInventors: Hideki Kitada, Nobuyuki Ohtsuka, Noriyoshi Shimizu, Yoshiyuki Nakao
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Publication number: 20070049024Abstract: An insulating film having a concave portion is formed on a semiconductor substrate. The inner surface of the concave portion and the upper surface of the insulating film are covered with an auxiliary film made of Cu alloy containing a first metal element other than Cu. A conductive member containing Cu as a main composition is deposited on the auxiliary film, the conductive member being embedded in the concave portion. Heat treatment is performed in an atmosphere containing P compound, Si compound or B compound. With this method, a content of element other than Cu in the conductive member can be reduced and a resistivity can be lowered.Type: ApplicationFiled: December 6, 2005Publication date: March 1, 2007Applicant: FUJITSU LIMITEDInventors: Yoshiyuki Nakao, Hideki Kitada, Nobuyuki Ohtsuka, Noriyoshi Shimizu
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Publication number: 20070048931Abstract: (a1) A concave portion is formed in an interlayer insulating film formed on a semiconductor substrate. (a2) A first film of Mn is formed by CVD, the first film covering the inner surface of the concave portion and the upper surface of the insulating film. (a3) Conductive material essentially consisting of Cu is deposited on the first film to embed the conductive material in the concave portion. (a4) The semiconductor substrate is annealed. During the period until a barrier layer is formed having also a function of improving tight adhesion, it is possible to ensure sufficient tight adhesion of wiring members and prevent peel-off of the wiring members.Type: ApplicationFiled: December 28, 2005Publication date: March 1, 2007Applicant: FUJITSU LIMITEDInventors: Noriyoshi Shimizu, Nobuyuki Ohtsuka, Hideki Kitada, Yoshiyuki Nakao
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Publication number: 20060145348Abstract: A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A conductive member is buried in the recess. A semiconductor device is provided whose interlayer insulating film can be worked easily even if it is made to have a low dielectric constant.Type: ApplicationFiled: February 28, 2006Publication date: July 6, 2006Applicant: Fujitsu LimitedInventors: Noriyoshi Shimizu, Yoshiyuki Nakao, Hiroki Kondo, Takashi Suzuki, Nobuyuki Nishikawa
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Patent number: 7042093Abstract: A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A conductive member is buried in the recess. A semiconductor device is provided whose interlayer insulating film can be worked easily even if it is made to have a low dielectric constant.Type: GrantFiled: January 28, 2003Date of Patent: May 9, 2006Assignee: Fujitsu LimitedInventors: Noriyoshi Shimizu, Yoshiyuki Nakao, Hiroki Kondo, Takashi Suzuki, Nobuyuki Nishikawa
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Patent number: 6992005Abstract: A semiconductor device having a multi-layered wiring structure containing a copper layer, comprises a first insulating film formed over a semiconductor substrate, a first copper pattern buried in the first insulating film, a cap layer formed on the first copper pattern and the first insulating film and made of a substance a portion of which formed on the first copper pattern has a smaller electrical resistance value than a portion formed on the first insulating film, second insulating films formed on the cap layer, and a second copper pattern buried in a hole or a trench, which is formed in the second insulating films on the first copper pattern; and connected electrically to the first copper pattern via the cap layer.Type: GrantFiled: April 7, 2004Date of Patent: January 31, 2006Assignee: Fujitsu LimitedInventors: Nobuyuki Ohtsuka, Noriyoshi Shimizu, Hisaya Sakai, Yoshiyuki Nakao, Hiroki Kondo, Takashi Suzuki
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Publication number: 20040188839Abstract: A semiconductor device having a multi-layered wiring structure containing a copper layer, comprises a first insulating film formed over a semiconductor substrate, a first copper pattern buried in the first insulating film, a cap layer formed on the first copper pattern and the first insulating film and made of a substance a portion of which formed on the first copper pattern has a smaller electrical resistance value than a portion formed on the first insulating film, second insulating films formed on the cap layer, and a second copper pattern buried in a hole or a trench, which is formed in the second insulating films on the first copper pattern; and connected electrically to the first copper pattern via the cap layer.Type: ApplicationFiled: April 7, 2004Publication date: September 30, 2004Applicant: FUJITSU LIMITEDInventors: Nobuyuki Ohtsuka, Noriyoshi Shimizu, Hisaya Sakai, Yoshiyuki Nakao, Hiroki Kondo, Takashi Suzuki
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Patent number: 6750541Abstract: A semiconductor device having a multi-layered wiring structure containing a copper layer, comprises a first insulating film formed over a semiconductor substrate, a first copper pattern buried in the first insulating film, a cap layer formed on the first copper pattern and the first insulating film and made of a substance a portion of which formed on the first copper pattern has a smaller electrical resistance value than a portion formed on the first insulating film, second insulating films formed on the cap layer, and a second copper pattern buried in a hole or a trench, which is formed in the second insulating films on the first copper pattern, and connected electrically to the first copper pattern via the cap layer.Type: GrantFiled: April 23, 2002Date of Patent: June 15, 2004Assignee: Fujitsu LimitedInventors: Nobuyuki Ohtsuka, Noriyoshi Shimizu, Hisaya Sakai, Yoshiyuki Nakao, Hiroki Kondo, Takashi Suzuki
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Publication number: 20040004287Abstract: A first insulating film is formed on a semiconductor substrate. A second insulating film made of insulating metal nitride is formed on the first insulating film. A recess is formed through the second insulating film and reaches a position deeper than an upper surface of the first insulating film. A conductive member is buried in the recess. A semiconductor device is provided whose interlayer insulating film can be worked easily even if it is made to have a low dielectric constant.Type: ApplicationFiled: January 28, 2003Publication date: January 8, 2004Applicant: FUJITSU LIMITEDInventors: Noriyoshi Shimizu, Yoshiyuki Nakao, Hiroki Kondo, Takashi Suzuki, Nobuyuki Nishikawa
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Publication number: 20020158338Abstract: A semiconductor device having a multi-layered wiring structure containing a copper layer, comprises a first insulating film formed over a semiconductor substrate, a first copper pattern buried in the first insulating film, a cap layer formed on the first copper pattern and the first insulating film and made of a substance a portion of which formed on the first copper pattern has a smaller electrical resistance value than a portion formed on the first insulating film, second insulating films formed on the cap layer, and a second copper pattern buried in a hole or a trench, which is formed in the second insulating films on the first copper pattern, and connected electrically to the first copper pattern via the cap layer.Type: ApplicationFiled: April 23, 2002Publication date: October 31, 2002Applicant: Fujitsu LimitedInventors: Nobuyuki Ohtsuka, Noriyoshi Shimizu, Hisaya Sakai, Yoshiyuki Nakao, Hiroki Kondo, Takashi Suzuki
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Patent number: 5667942Abstract: A resist pattern forming method which includes:an application step of applying a photoresist onto a semiconductor substrate,a prebake step of prebaking the photoresist in an atmosphere containing water vapor following the application of the photoresists to the substrate,an exposure step of exposing the photoresist to radiation following the prebake step,a heating step of heating the photoresist following the exposure step, anda development step of developing the photoresist following the heating step, whereby a large amount of water is imparted to and is therefore present in the resist film so as to obtain high dissolving speed of the exposed part of the resist into the developer, with the result of improving the resist sensitivity.Type: GrantFiled: July 15, 1996Date of Patent: September 16, 1997Assignee: Fujitsu LimitedInventors: Yoshiyuki Nakao, Minoru Hirose