Abstract: For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.

Abstract: The present invention provides a method and a system based on a multi-gate field effect transistor for sensing molecules in a gas or liquid sample. The said FET transistor comprises dual gate lateral electrodes (and optionally a back gate electrode) located on the two sides of an active region, and a sensing surface on top of the said active region. Appling voltages to the lateral gate electrodes, creates a conductive channel in the active region, wherein the width and the lateral position of the said channel can be controlled. Enhanced sensing sensitivity is achieved by measuring the channels conductivity at a plurality of positions in the lateral direction. The use of an array of the said FTE for electronic nose is also disclosed.

Abstract: The present invention provides a method and a system based on a multi-gate field effect transistor for sensing molecules in a gas or liquid sample. The said FET transistor comprises dual gate lateral electrodes (and optionally a back gate electrode) located on the two sides of an active region, and a sensing surface on top of the said active region. Appling voltages to the lateral gate electrodes, creates a conductive channel in the active region, wherein the width and the lateral position of the said channel can be controlled. Enhanced sensing sensitivity is achieved by measuring the channels conductivity at a plurality of positions in the lateral direction. The use of an array of the said FTE for electronic nose is also disclosed.

Abstract: Some demonstrative embodiments include an apparatus of a temperature sensor to sense temperature, the apparatus including a first pad on a silicon substrate; a second pad on the silicon substrate; a silicon nanowire having a first end coupled to the first pad and a second end coupled to the second pad, the silicon nanowire configured to drive a current between the first pad and the second pad, the current depending at least on the temperature; and a charged dielectric layer covering at least three sides of the silicon nanowire.

Abstract: For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.

Abstract: For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.

Abstract: A transistor (100), including a planar semiconducting substrate (36), a source (42) formed on the substrate, a first drain (102) formed on the substrate, and a second drain (104) formed on the substrate in a location physically separated from the first drain. At least one gate (38, 40) is formed on the substrate and is configured to selectably apply an electrical potential to the substrate in either a first spatial pattern, which causes a first conductive path (62) to be established within the substrate from the source to the first drain, or a second spatial pattern, which causes a second conductive path to be established within the substrate from the source to the second drain.

Abstract: A transistor (100), including a planar semiconducting substrate (36), a source (42) formed on the substrate, a first drain (102) formed on the substrate, and a second drain (104) formed on the substrate in a location physically separated from the first drain. At least one gate (38, 40) is formed on the substrate and is configured to selectably apply an electrical potential to the substrate in either a first spatial pattern, which causes a first conductive path (62) to be established within the substrate from the source to the first drain, or a second spatial pattern, which causes a second conductive path to be established within the substrate from the source to the second drain.

Abstract: For example, an Electrostatically Formed Nanowire (EFN) may include a source region; at least one drain region; a wire region configured to drive a current between the source and drain regions via a conductive channel; a first lateral-gate area extending along a first surface of the wire region between the source and drain regions; a second lateral-gate area extending along a second surface of the wire region between the source and drain regions; and a sensing area in opening in a backside of a silicon substrate under the wire region and the first and second lateral-gate areas, the sensing area configured to, in reaction to a predefined substance, cause a change in a conductivity of the conductive channel.

Abstract: Some demonstrative embodiments include an apparatus of a temperature sensor to sense temperature, the apparatus including a first pad on a silicon substrate; a second pad on the silicon substrate; a silicon nanowire having a first end coupled to the first pad and a second end coupled to the second pad, the silicon nanowire configured to drive a current between the first pad and the second pad, the current depending at least on the temperature; and a charged dielectric layer covering at least three sides of the silicon nanowire.

Abstract: The present invention provides a method and a system based on a multi-gate field effect transistor for sensing molecules in a gas or liquid sample. The said FET transistor comprises dual gate lateral electrodes (and optionally a back gate electrode) located on the two sides of an active region, and a sensing surface on top of the said active region. Appling voltages to the lateral gate electrodes, creates a conductive channel in the active region, wherein the width and the lateral position of the said channel can be controlled. Enhanced sensing sensitivity is achieved by measuring the channels conductivity at a plurality of positions in the lateral direction. The use of an array of the said FTE for electronic nose is also disclosed.

Abstract: The present invention provides a method and a system based on a multi-gate field effect transistor for sensing molecules in a gas or liquid sample. The said FET transistor comprises dual gate lateral electrodes (and optionally a back gate electrode) located on the two sides of an active region, and a sensing surface on top of the said active region. Applying voltages to the lateral gate electrodes, creates a conductive channel in the active region, wherein the width and the lateral position of the said channel can be controlled. Enhanced sensing sensitivity is achieved by measuring the channels conductivity at a plurality of positions in the lateral direction. The use of an array of the said FTE for electronic nose is also disclosed.

Abstract: An electrostatically formed nanowire transistor, includes a source, a drain, and multiple gates surrounding a doped silicon region. The gates include a top gate, a bottom gate, and side gates. The gates induce a channel in said doped silicon region. The channel has a width which is decreased by negative biasing of the side gates, and a height and vertical position controlled by the top and bottom gates.

Abstract: An electrostatically formed nanowire transistor, includes a source, a drain, and multiple gates surrounding a doped silicon region. The gates include a top gate, a bottom gate, and side gates. The gates induce a channel in said doped silicon region. The channel has a width which is decreased by negative biasing of the side gates, and a height and vertical position controlled by the top and bottom gates.

Abstract: A transistor (100), including a planar semiconducting substrate (36), a source (42) formed on the substrate, a first drain (102) formed on the substrate, and a second drain (104) formed on the substrate in a location physically separated from the first drain. At least one gate (38, 40) is formed on the substrate and is configured to selectably apply an electrical potential to the substrate in either a first spatial pattern, which causes a first conductive path (62) to be established within the substrate from the source to the first drain, or a second spatial pattern, which causes a second conductive path to be established within the substrate from the source to the second drain.

Abstract: An electrostatically formed nanowire transistor, includes a source, a drain, and multiple gates surrounding a doped silicon region. The gates include a top gate, a bottom gate, and side gates. The gates induce a channel in said doped silicon region. The channel has a width which is decreased by negative biasing of the side gates, and a height and vertical position controlled by the top and bottom gates.

Abstract: An electrostatically formed nanowire transistor, includes a source, a drain, and multiple gates surrounding a doped silicon region. The gates include a top gate, a bottom gate, and side gates. The gates induce a channel in said doped silicon region. The channel has a width which is decreased by negative biasing of the side gates, and a height and vertical position controlled by the top and bottom gates.

Abstract: The present invention provides a method and a system based on a multi-gate field effect transistor for sensing molecules in a gas or liquid sample. The said FET transistor comprises dual gate lateral electrodes (and optionally a back gate electrode) located on the two sides of an active region, and a sensing surface on top of the said active region. Applying voltages to the lateral gate electrodes, creates a conductive channel in the active region, wherein the width and the lateral position of the said channel can be controlled. Enhanced sensing sensitivity is achieved by measuring the channels conductivity at a plurality of positions in the lateral direction. The use of an array of the said FTE for electronic nose is also disclosed.

Abstract: An optoelectronic device is disclosed. The device comprises one or more modified photocatalytic units, and a semiconductor surface. The modified photocatalytic unit is attached to the semiconductor surface such that when light is absorbed by the photocatalytic unit, an electric field is generated at sufficient amount to induce charge carrier locomotion within the semiconductor. In some embodiments a plurality of photocatalytic unit is attached to the semiconductor surface in oriented manner. The optoelectronic device can be operative in dry environment.

Abstract: A monolithic semiconductor solar cell including a semiconductor layer including a plurality of pores, wherein walls of the pores are doped, forming vertical junctions between the walls of the pores and a bulk of the semiconductor, the pores each contain a conductor which is in electrical contact with the walls of the pores, and the conductors of the pores are electrically interconnected to provide an output voltage of the solar cell. A monolithic semiconductor solar cell including a semiconductor layer including a plurality of trenches, wherein walls of the trenches are doped, forming vertical junctions between the walls of the trenches and a bulk of the semiconductor, the trenches each contain a conductor which is in electrical contact with the walls of the trenches, and the conductors of the trenches are electrically interconnected to provide an output voltage of the solar cell. Related apparatus and methods are also described.