Patents by Inventor Yosuke Kajiwara

Yosuke Kajiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210218394
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, a gate electrode, a source electrode, a drain electrode, a conductive member, a gate terminal, and a first circuit. The semiconductor member includes a first semiconductor layer including a first partial region and including Alx1Ga1?x1N (0?x1?1), and a second semiconductor layer including Alx2Ga1?x2N (0<x2?1 and x1<x2). The first partial region is between the gate electrode and at least a portion of the conductive member in a first direction. The gate terminal is electrically connected to the gate electrode. The first circuit is configured to apply a first voltage to the conductive member based on a gate voltage applied to the gate terminal. The first voltage has a reverse polarity of a polarity of the gate voltage.
    Type: Application
    Filed: September 11, 2020
    Publication date: July 15, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiko KURAGUCHI, Yosuke KAJIWARA, Kentaro IKEDA
  • Patent number: 11043452
    Abstract: According to one embodiment, a semiconductor device includes first to fourth electrodes, a semiconductor layer, a first extension conductive layer, first and second electrode connection portions, and an insulating member. The first to fourth electrodes extend along a first direction. The first electrode is between the second and third electrodes in a second direction. The second direction crosses the first direction. The first extension conductive layer extends along the first direction and is electrically connected to the first electrode. The fourth electrode is between the first and third electrodes in the second direction. The first electrode connection portion is electrically connected to the first electrode. The second electrode connection portion is electrically connected to the second and fourth electrodes. The insulating member includes a first insulating portion. The first insulating portion is between the second electrode connection portion and a portion of the first electrode.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 22, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Masahiko Kuraguchi
  • Publication number: 20210184007
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, first and second insulating members, and a first member. The third electrode includes a first electrode portion. The first electrode portion is between the first and second electrodes. The first semiconductor layer includes first, second, third, fourth, and fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The first insulating member includes first and second insulating regions. The second insulating member includes first and second insulating portions. The first insulating portion is between the fourth partial region and the first insulating region. The second insulating portion is between the fifth partial region and the second insulating region. The second semiconductor layer includes first, second, and third semiconductor portions.
    Type: Application
    Filed: September 8, 2020
    Publication date: June 17, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke KAJIWARA, Masahiko KURAGUCHI, Akira MUKAI
  • Publication number: 20210167207
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, a first source electrode, a first gate electrode, a first drain electrode, a source pad part, a first source connection part, and an insulating part. The semiconductor member includes first and second semiconductor layers. The first gate electrode includes first to fourth portions. The first source electrode is between the first and second portions in a first direction, and is between the third and fourth portions in a second. The first drain electrode extends along the first direction. The first source electrode is between the third portion and the first drain electrode in the second direction. The first source connection part electrically connects the first source electrode and the source pad part. A portion of the first insulating region of the insulating part is between the first portion and the first source connection part.
    Type: Application
    Filed: September 8, 2020
    Publication date: June 3, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke KAJIWARA, Masahiko KURAGUCHI
  • Patent number: 11018248
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: May 25, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi
  • Patent number: 10964802
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third layers, and a first insulating layer. The first layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions. The second partial region is between the third and fifth partial regions. The first insulating layer includes first and second inter-layer regions. The second layer includes first and second intermediate regions. The first intermediate region is provided between the first partial region and the first inter-layer region. The second intermediate region is provided between the second partial region and the second inter-layer region. The third layer includes first to third nitride regions. The first inter-layer region is between the first intermediate region and the first nitride region. The second inter-layer region is between the second intermediate region and the second nitride region.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 30, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Akira Mukai, Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi
  • Publication number: 20210066486
    Abstract: According to one embodiment, a semiconductor device includes first to fourth semiconductor regions, and an insulating part. The third electrode is between the first and second electrodes in a first direction from the first electrode toward the second electrode. The first semiconductor region includes Alx1Ga1-x1N and includes first to fifth partial regions. A second direction from the first partial region toward the first electrode crosses the first direction. The second semiconductor region includes Alx2Ga1-x2N and includes sixth and seventh partial regions. The third semiconductor region includes Alx3Ga1-x3N and includes an eighth partial region between the fifth and seventh partial regions. The fourth semiconductor region includes Alx4Ga1-x4N and includes a first portion between the fifth and eighth partial regions. The fourth semiconductor region includes a first element not included the first to third semiconductor regions. The insulating part includes first to third insulating regions.
    Type: Application
    Filed: February 26, 2020
    Publication date: March 4, 2021
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yosuke KAJIWARA, Hiroshi ONO, Jumpei TAJIMA, Toshiki HIKOSAKA, Shinya NUNOUE, Masahiko KURAGUCHI
  • Patent number: 10937875
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, drain electrodes, a drain interconnect portion, and a drain conductive portion. The semiconductor member includes first and second semiconductor regions. The drain electrodes extend along a first direction, are arranged in a second direction crossing the first direction, and are provided at the first semiconductor region. A direction from the first semiconductor region toward the second semiconductor region is aligned with the first direction. The drain interconnect portion extends along the second direction and is electrically connected to the drain electrodes. The drain conductive portion is electrically connected to the drain interconnect portion. The drain conductive portion includes first and second conductive regions. A portion of the drain interconnect portion is between the first conductive region and the first semiconductor region in a third direction.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 2, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Aya Shindome, Masahiko Kuraguchi
  • Patent number: 10916646
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, and a first insulating film. The first semiconductor region includes a first partial region, a second partial region, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The second semiconductor region includes a sixth partial region and a seventh partial region. The third electrode overlaps the sixth and seventh partial regions. The first insulating film includes a portion provided between the third electrode and the third partial region, between the third electrode and the fourth partial region, between the third electrode and the fifth partial region, between the third electrode and the sixth partial region, and between the third electrode and the seventh partial region.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: February 9, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Daimotsu Kato, Toshiya Yonehara, Hiroshi Ono, Yosuke Kajiwara, Masahiko Kuraguchi, Tatsuo Shimizu
  • Patent number: 10910490
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to fourth semiconductor regions, a first layer including, and a first insulating layer. The first semiconductor region includes Alx1Ga1-x1N and includes first to fifth partial regions. The third partial region includes a first element including at least one selected from the group consisting of Mg, Zn, and C. The second semiconductor region includes Alx2Ga1-x2N and includes a sixth partial region and a seventh partial region. The third semiconductor region includes Alx3Ga1-x3N and includes an eighth partial region and a ninth partial region. The fourth semiconductor region includes Alx4Ga1-x4N and includes a tenth partial region and an eleventh partial region. The first layer includes AlyGa1-yN and includes a first portion provided between the third partial region and the third electrode. The first insulating layer includes a second portion provided between the first portion and the third electrode.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: February 2, 2021
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masahiko Kuraguchi, Yosuke Kajiwara, Aya Shindome, Hiroshi Ono, Daimotsu Kato, Akira Mukai, Toshiki Hikosaka, Jumpei Tajima
  • Publication number: 20200411675
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first nitride region, a second nitride region, and a first insulating film. The first nitride region includes Alx1Ga1-x1N. The first nitride region includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The second nitride region includes Alx2Ga1-x2N. The second nitride region includes sixth and seventh partial regions. The first insulating film includes a first insulating region and is between the third partial region and the third electrode. The third partial region has a first surface opposing the first insulating region. The fourth partial region has a second surface opposing the sixth partial region.
    Type: Application
    Filed: March 3, 2020
    Publication date: December 31, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Daimotsu KATO, Yosuke KAJIWARA, Akira MUKAI, Aya SHINDOME, Hiroshi ONO, Masahiko KURAGUCHI
  • Publication number: 20200373422
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, a first conductive part, first and second insulating layers. The third electrode includes first and second portions. The first portion is between the first electrode and the second electrode. The first semiconductor layer includes first, second, third, fourth and fifth partial regions. The third partial region is between the first and second partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The second semiconductor layer includes first and second semiconductor regions. The first conductive part is electrically connected to the first electrode. The first insulating layer includes a first insulating portion. The second insulating layer includes first and second insulating regions.
    Type: Application
    Filed: February 25, 2020
    Publication date: November 26, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masahiko KURAGUCHI, Yosuke KAJIWARA, Aya SHINDOME, Hiroshi ONO, Daimotsu KATO, Akira MUKAI
  • Publication number: 20200335587
    Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, and a first compound member. A position of the third electrode is between a position of the second electrode and a position of the first electrode. The first semiconductor layer includes first, second, third, fourth, and fifth partial regions. The fourth partial region is between the third and first partial regions. The fifth partial region is between the second and third partial regions. The second semiconductor layer includes first, second, and third semiconductor regions. The third semiconductor region is between the first partial region and the first electrode. The first compound member includes first compound portions between the third semiconductor region and the first electrode. A portion of the first electrode is between one of the first compound portions and an other one of the first compound portions.
    Type: Application
    Filed: February 11, 2020
    Publication date: October 22, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Hiroshi ONO, Akira MUKAI, Yosuke KAJIWARA, Daimotsu KATO, Aya SHINDOME, Masahiko KURAGUCHI
  • Publication number: 20200328146
    Abstract: According to one embodiment, a semiconductor device includes first to fourth electrodes, a semiconductor layer, a first extension conductive layer, first and second electrode connection portions, and an insulating member. The first to fourth electrodes extend along a first direction. The first electrode is between the second and third electrodes in a second direction. The second direction crosses the first direction. The first extension conductive layer extends along the first direction and is electrically connected to the first electrode. The fourth electrode is between the first and third electrodes in the second direction. The first electrode connection portion is electrically connected to the first electrode. The second electrode connection portion is electrically connected to the second and fourth electrodes. The insulating member includes a first insulating portion. The first insulating portion is between the second electrode connection portion and a portion of the first electrode.
    Type: Application
    Filed: February 26, 2020
    Publication date: October 15, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke KAJIWARA, Masahiko KURAGUCHI
  • Publication number: 20200295169
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third nitride regions, and first and second insulating films. The first nitride region includes AlxiGai-x1N, and includes first and second partial regions, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The first nitride region includes first to fifth partial regions. The second nitride region includes Alx2Ga1-x2N, and sixth and seventh partial regions. At least a portion of the third electrode is between the sixth and seventh partial regions. The first insulating film includes silicon and oxygen and includes first and second insulating regions. The third nitride region includes Alx3Ga1-x3N, and first to seventh portions. The second insulating film includes silicon and oxygen and includes third to seventh insulating regions.
    Type: Application
    Filed: September 12, 2019
    Publication date: September 17, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Daimotsu KATO, Yosuke Kajiwara, Akira Mukai, Aya Shindome, Hiroshi Ono, Masahiko Kuraguchi
  • Patent number: 10714608
    Abstract: According to one embodiment, a semiconductor device includes first and second regions, a first insulating portion, and first, second, and third electrodes. The first region includes first and second partial regions, and a third partial region between the first and second partial regions. The second region includes fourth and fifth partial regions. The fourth partial region overlaps the first partial region. The fifth partial region overlaps the second partial region. The first insulating portion includes first, second, and third insulating regions. The first insulating region is provided between the second insulating region and the third partial region and between the third insulating region and the third partial region. The first electrode is electrically connected to the fourth partial region. The second electrode is away from the first electrode and is electrically connected to the fifth partial region. The third electrode is provided between the first and second electrodes.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: July 14, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masahiko Kuraguchi, Yosuke Kajiwara, Aya Shindome, Hiroshi Ono, Daimotsu Kato, Akira Mukai
  • Publication number: 20200220003
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to fourth semiconductor regions, a first layer including, and a first insulating layer. The first semiconductor region includes Alx1Ga1-x1N and includes first to fifth partial regions. The third partial region includes a first element including at least one selected from the group consisting of Mg, Zn, and C. The second semiconductor region includes Alx2Ga1-x2N and includes a sixth partial region and a seventh partial region. The third semiconductor region includes Alx3Ga1-x3N and includes an eighth partial region and a ninth partial region. The fourth semiconductor region includes Alx4Ga1-x4N and includes a tenth partial region and an eleventh partial region. The first layer includes AlyGa1-yN and includes a first portion provided between the third partial region and the third electrode. The first insulating layer includes a second portion provided between the first portion and the third electrode.
    Type: Application
    Filed: September 10, 2019
    Publication date: July 9, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masahiko Kuraguchi, Yosuke Kajiwara, Aya Shindome, Hiroshi Ono, Daimotsu Kato, Akira Mukai, Toshiki Hikosaka, Jumpei Tajima
  • Patent number: 10644143
    Abstract: According to one embodiment, a semiconductor device includes first and second semiconductor layers, first, second, and third electrodes, and first and second insulating portions. The first semiconductor layer includes first, second, and third semiconductor regions. The second semiconductor layer includes first to sixth partial regions. The first electrode is electrically connected to the first partial region. The second electrode is electrically connected to the second partial region. A position of the third electrode is between positions of the first and second electrodes in a second direction. A first direction crosses the second direction from the first to second semiconductor regions. The first insulating portion is provided between the third semiconductor region and the third electrode and between the third partial region and the third electrode in the first direction. The fourth partial region is between the second insulating portion and the second semiconductor region in the first direction.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: May 5, 2020
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Aya Shindome, Masahiko Kuraguchi
  • Publication number: 20200135870
    Abstract: According to one embodiment, a semiconductor device includes a semiconductor member, drain electrodes, a drain interconnect portion, and a drain conductive portion. The semiconductor member includes first and second semiconductor regions. The drain electrodes extend along a first direction, are arranged in a second direction crossing the first direction, and are provided at the first semiconductor region. A direction from the first semiconductor region toward the second semiconductor region is aligned with the first direction. The drain interconnect portion extends along the second direction and is electrically connected to the drain electrodes. The drain conductive portion is electrically connected to the drain interconnect portion. The drain conductive portion includes first and second conductive regions. A portion of the drain interconnect portion is between the first conductive region and the first semiconductor region in a third direction.
    Type: Application
    Filed: September 10, 2019
    Publication date: April 30, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke Kajiwara, Aya Shindome, Masahiko Kuraguchi
  • Publication number: 20200027976
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third layers, and a first insulating layer. The first layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions. The second partial region is between the third and fifth partial regions. The first insulating layer includes first and second inter-layer regions. The second layer includes first and second intermediate regions. The first intermediate region is provided between the first partial region and the first inter-layer region. The second intermediate region is provided between the second partial region and the second inter-layer region. The third layer includes first to third nitride regions. The first inter-layer region is between the first intermediate region and the first nitride region. The second inter-layer region is between the second intermediate region and the second nitride region.
    Type: Application
    Filed: March 11, 2019
    Publication date: January 23, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Akira MUKAI, Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi