Patents by Inventor Yosuke Kajiwara

Yosuke Kajiwara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200027976
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first to third layers, and a first insulating layer. The first layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions. The second partial region is between the third and fifth partial regions. The first insulating layer includes first and second inter-layer regions. The second layer includes first and second intermediate regions. The first intermediate region is provided between the first partial region and the first inter-layer region. The second intermediate region is provided between the second partial region and the second inter-layer region. The third layer includes first to third nitride regions. The first inter-layer region is between the first intermediate region and the first nitride region. The second inter-layer region is between the second intermediate region and the second nitride region.
    Type: Application
    Filed: March 11, 2019
    Publication date: January 23, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Akira MUKAI, Yosuke Kajiwara, Daimotsu Kato, Masahiko Kuraguchi
  • Publication number: 20200027978
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor layers, a nitride layer, and an oxide layer. A direction from the second electrode toward the first electrode is aligned with a first direction. A position in the first direction of the third electrode is between the first electrode and the second electrode in the first direction. The first semiconductor layer includes first to fifth partial regions. The first partial region is between the fourth and third partial regions in the first direction. The second partial region is between the third and fifth partial regions in the first direction. The nitride layer includes first and second nitride regions. The second semiconductor layer includes first and second semiconductor regions. The oxide layer includes silicon and oxygen. The oxide layer includes first to third oxide regions.
    Type: Application
    Filed: March 5, 2019
    Publication date: January 23, 2020
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke KAJIWARA, Daimotsu KATO, Masahiko KURAGUCHI
  • Publication number: 20190386127
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, first and second semiconductor regions, and a first insulating film. The first semiconductor region includes a first partial region, a second partial region, a third partial region between the first and second partial regions, a fourth partial region between the first and third partial regions, and a fifth partial region between the third and second partial regions. The second semiconductor region includes a sixth partial region and a seventh partial region. The third electrode overlaps the sixth and seventh partial regions. The first insulating film includes a portion provided between the third electrode and the third partial region, between the third electrode and the fourth partial region, between the third electrode and the fifth partial region, between the third electrode and the sixth partial region, and between the third electrode and the seventh partial region.
    Type: Application
    Filed: March 11, 2019
    Publication date: December 19, 2019
    Applicants: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Daimotsu KATO, Toshiya Yonehara, Hiroshi Ono, Yosuke Kajiwara, Masahiko Kuraguchi, Tatsuo Shimizu
  • Publication number: 20190371928
    Abstract: According to one embodiment, a semiconductor device includes first and second regions, a first insulating portion, and first, second, and third electrodes. The first region includes first and second partial regions, and a third partial region between the first and second partial regions. The second region includes fourth and fifth partial regions. The fourth partial region overlaps the first partial region. The fifth partial region overlaps the second partial region. The first insulating portion includes first, second, and third insulating regions. The first insulating region is provided between the second insulating region and the third partial region and between the third insulating region and the third partial region. The first electrode is electrically connected to the fourth partial region. The second electrode is away from the first electrode and is electrically connected to the fifth partial region. The third electrode is provided between the first and second electrodes.
    Type: Application
    Filed: March 5, 2019
    Publication date: December 5, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Masahiko KURAGUCHI, Yosuke Kajiwara, Aya Shindome, Hiroshi Ono, Daimotsu Kato, Akira Mukai
  • Publication number: 20190371927
    Abstract: According to one embodiment, a semiconductor device includes first and second semiconductor layers, first, second, and third electrodes, and first and second insulating portions. The first semiconductor layer includes first, second, and third semiconductor regions. The second semiconductor layer includes first to sixth partial regions. The first electrode is electrically connected to the first partial region. The second electrode is electrically connected to the second partial region. A position of the third electrode is between positions of the first and second electrodes in a second direction. A first direction crosses the second direction from the first to second semiconductor regions. The first insulating portion is provided between the third semiconductor region and the third electrode and between the third partial region and the third electrode in the first direction. The fourth partial region is between the second insulating portion and the second semiconductor region in the first direction.
    Type: Application
    Filed: February 25, 2019
    Publication date: December 5, 2019
    Applicants: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Yosuke KAJIWARA, Aya Shindome, Masahiko Kuraguchi
  • Patent number: 10373833
    Abstract: A semiconductor device of an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a larger bandgap than the first GaN-based semiconductor layer, a source electrode provided on the second GaN-based semiconductor layer, a drain electrode provided on the second GaN-based semiconductor layer, a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer, a gate insulating film provided on a surface of the recess, and a gate electrode provided on the gate insulating film and having an end portion in a gate width direction, located in the recess.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: August 6, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Aya Shindome, Masahiko Kuraguchi, Hisashi Saito, Shigeto Fukatsu, Miki Yumoto, Yosuke Kajiwara
  • Patent number: 10243058
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer including a nitride semiconductor, a first electrode separated from the first semiconductor layer in a first direction, and a first insulating film including silicon and oxygen and being provided between the first semiconductor layer and the first electrode. The first insulating film has a first thickness in the first direction. The first insulating film includes a first position, and a distance between the first position and the first semiconductor layer is ½ of the first thickness. A first hydrogen concentration of hydrogen at the first position is 2.5×1019 atoms/cm3 or less.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: March 26, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiya Yonehara, Hisashi Saito, Yosuke Kajiwara, Daimotsu Kato, Tatsuo Shimizu, Yasutaka Nishida
  • Publication number: 20190088771
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first region, and a first insulating layer. The first electrode includes a first electrode portion. The first region contains Ga and N. The first region includes a first subregion, a second subregion, and a third subregion. The first subregion and the third subregion contain at least one first element selected from the group consisting of Ar, B, P, N, and Fe. The first subregion is located between the first electrode portion and the second subregion in a first direction. The second subregion does not contain the first element, or concentration of the first element in the second subregion is lower than concentration of the first element in the first subregion and lower than concentration of the first element in the third subregion. The first insulating layer is provided between the first electrode and the first region.
    Type: Application
    Filed: February 21, 2018
    Publication date: March 21, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masahiko Kuraguchi, Yosuke Kajiwara, Miki Yumoto, Hiroshi Ono
  • Patent number: 10109715
    Abstract: A semiconductor device according to an embodiment includes: a substrate having a first plane and a second plane provided on the opposite side of the first plane; a first nitride semiconductor layer provided on the first plane; source electrodes provided on the first nitride semiconductor layer; drain electrodes provided on the first nitride semiconductor layer, each of the drain electrodes provided between the source electrodes; gate electrodes provided on the first nitride semiconductor layer, each of the gate electrodes provided between each of the source electrodes and each of the drain electrodes; a first wire provided on the second plane and electrically connected to the source electrodes; a second wire electrically connected to the drain electrodes; a third wire provided on the second plane and electrically connected to the gate electrodes; and an insulating interlayer provided between the first nitride semiconductor layer and the second wire.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 23, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Kajiwara, Kentaro Ikeda, Hisashi Saito, Masahiko Kuraguchi
  • Publication number: 20180261681
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer including a nitride semiconductor, a first electrode separated from the first semiconductor layer in a first direction, and a first insulating film including silicon and oxygen and being provided between the first semiconductor layer and the first electrode. The first insulating film has a first thickness in the first direction. The first insulating film includes a first position, and a distance between the first position and the first semiconductor layer is ½ of the first thickness. A first hydrogen concentration of hydrogen at the first position is 2.5×1019 atoms/cm3 or less.
    Type: Application
    Filed: August 21, 2017
    Publication date: September 13, 2018
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Toshiya YONEHARA, Hisashi SAITO, Yosuke KAJIWARA, Daimotsu KATO, Tatsuo SHIMIZU, Yasutaka NISHIDA
  • Publication number: 20170278934
    Abstract: A semiconductor device according to an embodiment includes: a substrate having a first plane and a second plane provided on the opposite side of the first plane; a first nitride semiconductor layer provided on the first plane; source electrodes provided on the first nitride semiconductor layer; drain electrodes provided on the first nitride semiconductor layer, each of the drain electrodes provided between the source electrodes; gate electrodes provided on the first nitride semiconductor layer, each of the gate electrodes provided between each of the source electrodes and each of the drain electrodes; a first wire provided on the second plane and electrically connected to the source electrodes; a second wire electrically connected to the drain electrodes; a third wire provided on the second plane and electrically connected to the gate electrodes; and an insulating interlayer provided between the first nitride semiconductor layer and the second wire.
    Type: Application
    Filed: December 28, 2016
    Publication date: September 28, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yosuke KAJIWARA, Kentaro IKEDA, Hisashi SAITO, Masahiko KURAGUCHI
  • Patent number: 9484421
    Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, a plurality of source electrodes provided on the nitride semiconductor layer, a plurality of drain electrodes, a plurality of gate electrodes, a first interconnection having a first distance from the nitride semiconductor layer and electrically connecting the source electrodes, a second interconnection electrically connecting the gate electrodes, and a third interconnection having a third distance from the nitride semiconductor layer and electrically connecting the drain electrodes. Each of the drain electrodes are provided between the source electrodes. Each of the gate electrodes are provided between each of the source electrodes and each of the drain electrodes. The third distance is larger than the first distance.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: November 1, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Kajiwara, Kentaro Ikeda, Hisashi Saito, Masahiko Kuraguchi
  • Publication number: 20160284831
    Abstract: A semiconductor device of an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a larger bandgap than the first GaN-based semiconductor layer, a source electrode provided on the second GaN-based semiconductor layer, a drain electrode provided on the second GaN-based semiconductor layer, a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer, a gate insulating film provided on a surface of the recess, and a gate electrode provided on the gate insulating film and having an end portion in a gate width direction, located in the recess.
    Type: Application
    Filed: February 29, 2016
    Publication date: September 29, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Aya SHINDOME, Masahiko KURAGUCHI, Hisashi SAITO, Shigeto FUKATSU, Miki YUMOTO, Yosuke KAJIWARA
  • Publication number: 20160087052
    Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer, a plurality of source electrodes provided on the nitride semiconductor layer, a plurality of drain electrodes, a plurality of gate electrodes, a first interconnection having a first distance from the nitride semiconductor layer and electrically connecting the source electrodes, a second interconnection electrically connecting the gate electrodes, and a third interconnection having a third distance from the nitride semiconductor layer and electrically connecting the drain electrodes. Each of the drain electrodes are provided between the source electrodes. Each of the gate electrodes are provided between each of the source electrodes and each of the drain electrodes. The third distance is larger than the first distance.
    Type: Application
    Filed: July 28, 2015
    Publication date: March 24, 2016
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yosuke KAJIWARA, Kentaro Ikeda, Hisashi Saito, Masahiko Kuraguchi
  • Patent number: 8604571
    Abstract: The thermoelectric conversion efficiency of a thermoelectric conversion device is increased by increasing the figure of merit of a spin-Seebeck effect element. An inverse spin-Hall effect material is provided to at least one end of a thermal spin-wave spin current generating material made of a magnetic dielectric material so that a thermal spin-wave spin current is converted to generate a voltage in the above described inverse spin-Hall effect material when there is a temperature gradient in the above described thermal spin-wave spin current generating material and a magnetic field is applied using a magnetic field applying means.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: December 10, 2013
    Assignee: Tohoku University
    Inventors: Kenichi Uchida, Yosuke Kajiwara, Hiroyasu Nakayama, Eiji Saitoh
  • Patent number: 8254163
    Abstract: A concrete means for making transmission over long distances possible using a spin-wave spin current is provided in a spintronic device and an information transmitting method. At least one metal electrode made of any of Pt, Au, Pd, Ag, Bi, alloys of these, or elements having an f-orbital are provided on top of a magnetic dielectric layer and, so that spin-wave spin current—pure spin current exchange is carried out at the interface between the above described magnetic dielectric layer and the above described metal electrode.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: August 28, 2012
    Assignee: Keio University
    Inventors: Yosuke Kajiwara, Kenichi Uchida, Kazuya Ando, Eiji Saitoh
  • Patent number: 8203191
    Abstract: The invention relates to a spin current thermal conversion device and a thermoelectric conversion device, with which a spin current is thermally generated, and its concrete application is realized. A temperature gradient creating means which creates a temperature gradient in a thermal spin current generating member is provided in a thermal spin current generating member made of either a ferromagnetic member or a conductive member containing a ferromagnetic substance.
    Type: Grant
    Filed: November 17, 2008
    Date of Patent: June 19, 2012
    Assignee: Keio University
    Inventors: Kenichi Uchida, Kazuya Harii, Yosuke Kajiwara, Eiji Saitoh
  • Publication number: 20110084349
    Abstract: The thermoelectric conversion efficiency of a thermoelectric conversion device is increased by increasing the figure of merit of a spin-Seebeck effect element. An inverse spin-Hall effect material is provided to at least one end of a thermal spin-wave spin current generating material made of a magnetic dielectric material so that a thermal spin-wave spin current is converted to generate a voltage in the above described inverse spin-Hall effect material when there is a temperature gradient in the above described thermal spin-wave spin current generating material and a magnetic field is applied using a magnetic field applying means.
    Type: Application
    Filed: June 5, 2009
    Publication date: April 14, 2011
    Applicant: KEIO UNIVERSITY
    Inventors: Kenichi Uchida, Yosuke Kajiwara, Hiroyasu Nakayama, Eiji Saitoh
  • Publication number: 20110075476
    Abstract: A concrete means for making transmission over long distances possible using a spin-wave spin current is provided in a spintronic device and an information transmitting method. At least one metal electrode made of any of Pt, Au, Pd, Ag, Bi, alloys of these, or elements having an f-orbital are provided on top of a magnetic dielectric layer and, so that spin-wave spin current—pure spin current exchange is carried out at the interface between the above described magnetic dielectric layer and the above described metal electrode.
    Type: Application
    Filed: June 4, 2009
    Publication date: March 31, 2011
    Applicant: KEIO UNIVERSITY
    Inventors: Yosuke Kajiwara, Kenichi Uchida, Kazuya Ando, Eiji Saitoh
  • Publication number: 20100276770
    Abstract: The invention relates to a spin current thermal conversion device and a thermoelectric conversion device, with which a spin current is thermally generated, and its concrete application is realized. A temperature gradient creating means which creates a temperature gradient in a thermal spin current generating member is provided in a thermal spin current generating member made of either a ferromagnetic member or a conductive member containing a ferromagnetic substance.
    Type: Application
    Filed: November 17, 2008
    Publication date: November 4, 2010
    Applicant: KEIO UNIVERSITY
    Inventors: Kenichi Uchida, Kazuya Harii, Yosuke Kajiwara, Eiji Saitoh