Patents by Inventor Yosuke Komori
Yosuke Komori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240132432Abstract: Provided is a compound represented by Formula (1A) below wherein the symbols are as defined in the description: Also disclosed are a composition containing at least one of the compound and a formed article of the compound.Type: ApplicationFiled: December 18, 2023Publication date: April 25, 2024Applicants: Kyoto University, DAIKIN INDUSTRIES, LTD.Inventors: Tomoki OGOSHI, Katsuto ONISHI, Shuhei YAMAGUCHI, Yuko SHIOTANI, Masaji KOMORI, Hirokazu AOYAMA, Yosuke KISHIKAWA, Akiyoshi YAMAUCHI
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Patent number: 11964621Abstract: A vehicle seatbelt device of an embodiment includes a recognizer that recognizes circumstances around a vehicle, a steering operator that is able to adjust steering of the vehicle, a vibrator that causes a portion of the steering operator to vibrate, a seatbelt that restrains a portion of the body of an occupant of the vehicle, a tension adjustment mechanism that is able to adjust the tension of the seatbelt, and a controller that controls the vibrator and the tension adjustment mechanism on the basis of the circumstances recognized by the recognizer.Type: GrantFiled: January 27, 2022Date of Patent: April 23, 2024Assignee: HONDA MOTOR CO., LTD.Inventors: Shinsuke Odai, Yuji Yasui, Kenji Komori, Yosuke Sakamoto, Yosuke Koike, Kenshi Torikai
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Publication number: 20240092061Abstract: A joined article including: a resin (1) having a linear expansion coefficient at 30° C. to 200° C. of 17 ppm/° C. or higher and a thickness of 5 to 100 ?m; and a metal joined to a surface of the resin (1) and having a thickness of 5 to 50 ?m. The resin (1) includes a heat-affected layer that is close to the metal and that occupies 80% or less of the thickness of the resin (1), and the joined article is a dielectric material for a substrate. Also disclosed is a substrate including the joined article and a resin (2) stacked on the joined article.Type: ApplicationFiled: October 27, 2023Publication date: March 21, 2024Applicants: THE UNIVERSITY OF TOKYO, DAIKIN INDUSTRIES, LTD.Inventors: Keisuke NAGATO, Kota AONO, Yusuke EBIHARA, Masayuki NAKAO, Yuki UEDA, Shingo OKUNO, Hirokazu KOMORI, Akiyoshi YAMAUCHI, Yosuke KISHIKAWA
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Patent number: 11923299Abstract: A semiconductor device according to the present embodiment comprises a first metallic line. The first metallic line is provided above a substrate and extends in a first direction with a first width. At least one second metallic line is connected to the first metallic line and extends in a second direction from the first metallic line with a second width that is smaller than the first width. A dummy metallic line is arranged adjacently to the at least one second metallic line, connected to the first metallic line, and extends in the second direction from the first metallic line. The dummy metallic line is not electrically connected to lines other than the first metallic line.Type: GrantFiled: August 23, 2022Date of Patent: March 5, 2024Assignee: Kioxia CorporationInventors: Takao Sueyama, Yosuke Komori
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Patent number: 11884110Abstract: A tire includes a surface geometry arrangement on a surface of a sidewall portion. The surface geometry arrangement includes a ridge pair in which two ridges bend so as to intersect each other a multiple number of times.Type: GrantFiled: November 10, 2020Date of Patent: January 30, 2024Assignee: SUMITOMO RUBBER INDUSTRIES, LTD.Inventor: Yosuke Komori
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Publication number: 20240008276Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: ApplicationFiled: September 12, 2023Publication date: January 4, 2024Applicant: KIOXIA CORPORATIONInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KITO, Masaru KIDOH, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Junya MATSUNAMI, Tomoko FUJIWARA, Hideaki AOCHI, Ryouhei KIRISAWA, Yoshimasa MIKAJIRI, Shigeto OOTA
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Patent number: 11844218Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: GrantFiled: June 17, 2022Date of Patent: December 12, 2023Assignee: KIOXIA CORPORATIONInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
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Patent number: 11792992Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: GrantFiled: January 14, 2022Date of Patent: October 17, 2023Assignee: Kioxia CorporationInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Publication number: 20230146470Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritahle memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of colunmar portions a charge storage layer formed to surround the side surfaces of the columnar portions: and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: ApplicationFiled: December 30, 2022Publication date: May 11, 2023Applicant: KIOXIA CORPORATIONInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KIDOH, Masaru KITO, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Hideaki AOCHI
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Patent number: 11574926Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions a charge storage layer formed to surround the side surfaces of the columnar portions: and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: GrantFiled: October 12, 2021Date of Patent: February 7, 2023Assignee: KIOXIA CORPORATIONInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
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Patent number: 11535066Abstract: A tire comprises a tread portion axially divided into four land regions. The tire has a mounting direction to a vehicle and the land regions 4 include a widest outboard middle land region. The outboard middle land region is provided with first, second and third inclined grooves. The first inclined groove extends from a crown main groove and terminates within the outboard middle land region. The second inclined groove has its both ends terminated within the outboard middle land region. The third inclined groove intersects the first and second inclined grooves.Type: GrantFiled: May 21, 2020Date of Patent: December 27, 2022Assignee: SUMITOMO RUBBER INDUSTRIES, LTD.Inventors: Yosuke Komori, Hiroshi Yamaoka, Yuta Sakakibara
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Publication number: 20220399267Abstract: A semiconductor device according to the present embodiment comprises a first metallic line. The first metallic line is provided above a substrate and extends in a first direction with a first width. At least one second metallic line is connected to the first metallic line and extends in a second direction from the first metallic line with a second width that is smaller than the first width. A dummy metallic line is arranged adjacently to the at least one second metallic line, connected to the first metallic line, and extends in the second direction from the first metallic line. The dummy metallic line is not electrically connected to lines other than the first metallic line.Type: ApplicationFiled: August 23, 2022Publication date: December 15, 2022Applicant: Kioxia CorporationInventors: Takao SUEYAMA, Yosuke KOMORI
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Publication number: 20220320138Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: ApplicationFiled: June 17, 2022Publication date: October 6, 2022Applicant: KIOXIA CORPORATIONInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KIDOH, Masaru KITO, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Hideaki AOCHI
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Patent number: 11456250Abstract: A semiconductor device according to the present embodiment comprises a first metallic line. The first metallic line is provided above a substrate and extends in a first direction with a first width. At least one second metallic line is connected to the first metallic line and extends in a second direction from the first metallic line with a second width that is smaller than the first width. A dummy metallic line is arranged adjacently to the at least one second metallic line, connected to the first metallic line, and extends in the second direction from the first metallic line. The dummy metallic line is not electrically connected to lines other than the first metallic line.Type: GrantFiled: August 25, 2020Date of Patent: September 27, 2022Assignee: Kioxia CorporationInventors: Takao Sueyama, Yosuke Komori
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Patent number: 11393840Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: GrantFiled: December 11, 2019Date of Patent: July 19, 2022Assignee: KIOXIA CORPORATIONInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
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Publication number: 20220139955Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: ApplicationFiled: January 14, 2022Publication date: May 5, 2022Applicant: Kioxia CorporationInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KITO, Masaru KIDOH, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Junya MATSUNAMI, Tomoko FUJIWARA, Hideaki AOCHI, Ryouhei KIRISAWA, Yoshimasa MIKAJIRI, Shigeto OOTA
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Patent number: 11257842Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: GrantFiled: April 15, 2020Date of Patent: February 22, 2022Assignee: Kioxia CorporationInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Publication number: 20220028892Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions a charge storage layer formed to surround the side surfaces of the columnar portions: and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: ApplicationFiled: October 12, 2021Publication date: January 27, 2022Applicant: KIOXIA CORPORATIONInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KIDOH, Masaru KITO, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Hideaki AOCHI
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Publication number: 20210280508Abstract: A semiconductor device according to the present embodiment comprises a first metallic line. The first metallic line is provided above a substrate and extends in a first direction with a first width. At least one second metallic line is connected to the first metallic line and extends in a second direction from the first metallic line with a second width that is smaller than the first width. A dummy metallic line is arranged adjacently to the at least one second metallic line, connected to the first metallic line, and extends in the second direction from the first metallic line. The dummy metallic line is not electrically connected to lines other than the first metallic line.Type: ApplicationFiled: August 25, 2020Publication date: September 9, 2021Applicant: Kioxia CorporationInventors: Takao SUEYAMA, Yosuke KOMORI
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Patent number: RE49152Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.Type: GrantFiled: July 10, 2020Date of Patent: July 26, 2022Assignee: Kioxia CorporationInventors: Ryota Katsumata, Hideaki Aochi, Hiroyasu Tanaka, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota