Patents by Inventor Yosuke Komori
Yosuke Komori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8748971Abstract: A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.Type: GrantFiled: April 5, 2013Date of Patent: June 10, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Yoshiaki Fukuzumi, Yosuke Komori, Megumi Ishiduki, Tomoko Fujiwara, Junya Matsunami, Ryouhei Kirisawa
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Patent number: 8728919Abstract: A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.Type: GrantFiled: December 21, 2012Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Megumi Ishiduki, Yosuke Komori, Hiroyasu Tanaka, Ryota Katsumata, Hideaki Aochi
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Patent number: 8729623Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of insulating layers, which are alternately stacked, and diffusion suppressing layers each provided between each of the plurality of electrode layers and each of the plurality of insulating layers; and a memory film provided on a side wall of a hole penetrating the stacked body in a stacking direction. Each of the plurality of electrode layers is a first semiconductor layer containing a first impurity element. The diffusion suppressing layer is a second semiconductor layer containing a second impurity element which is different from the first impurity element. The diffusion suppressing layer is a film having an effect of suppressing diffusion of the first impurity element.Type: GrantFiled: March 19, 2012Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tomo Ohsawa, Yosuke Komori
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Patent number: 8729624Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: GrantFiled: January 14, 2013Date of Patent: May 20, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
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Patent number: 8723247Abstract: According to one embodiment, a semiconductor memory device includes a plurality of gate electrode films arranged parallel to each other along a direction, a semiconductor member extending in the direction, and passing through the plurality of gate electrode films, and a charge storage film provided between the gate electrode films and the semiconductor member. Protrusions are provided projecting along the direction at the ends of the gate electrode films in opposition to the semiconductor member. A gaseous layer is formed in a part of a gap between the gate electrode films.Type: GrantFiled: August 26, 2011Date of Patent: May 13, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yosuke Komori, Daigo Ichinose
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Publication number: 20140117434Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: ApplicationFiled: January 8, 2014Publication date: May 1, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Patent number: 8653577Abstract: A nonvolatile semiconductor memory device includes: a stacked body in which insulating films and electrode films are alternately stacked; selection gate electrodes provided on the stacked body; bit lines provided on the selection gate electrodes; semiconductor pillars; connective members separated from one another; and a charge storage layer provided between the electrode film and the semiconductor pillar. One of the connective members is connected between a lower part of one of the semiconductor pillars and a lower part of another of the semiconductor pillars. The one of the semiconductor pillars passes through one of the selection gate electrodes and is connected to one of the bit lines, and the another of the semiconductor pillars passes through another of the selection gate electrodes and is connected to another of the bit lines.Type: GrantFiled: July 1, 2009Date of Patent: February 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Fukuzumi, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Masaru Kito, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh
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Patent number: 8654586Abstract: A nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a multilayer structure including electrode films and inter-electrode insulating films alternately stacked in a first direction; a semiconductor pillar piercing the multilayer structure in the first direction; a memory layer provided between the semiconductor pillar and the electrode films; an inner insulating film provided between the memory layer and the semiconductor pillar; an outer insulating film provided between the memory layer and the electrode films; and a wiring electrically connected to the first semiconductor pillar. In an erasing operation, the control unit sets the first wiring at a first potential and sets the electrode film at a second potential lower than the first potential, and then sets the first wiring at a third potential and sets the electrode film at a fourth potential higher than the third potential.Type: GrantFiled: January 9, 2013Date of Patent: February 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Patent number: 8653582Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: GrantFiled: March 16, 2010Date of Patent: February 18, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Publication number: 20140027838Abstract: According to one embodiment, the stair array includes a deep portion, one stair, and a plurality of stairs. The one stair is provided next to the deepest portion in the first direction and has a level difference of one step with the deepest portion. Each of the stairs has a level difference of a plurality of steps with a stair next in the first direction.Type: ApplicationFiled: July 25, 2013Publication date: January 30, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Nozomi Kido, Yosuke Komori
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Patent number: 8569133Abstract: A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells.Type: GrantFiled: February 6, 2012Date of Patent: October 29, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi
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Patent number: 8541866Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of stacked component units stacked in a first direction, each of the stacked component units including a first conducting film made of a semiconductor of a first conductivity type provided perpendicular to the first direction and a first insulating film stacked in the first direction with the first conducting film; a semiconductor pillar piercing the stacked structural unit in the first direction and including a conducting region of a second conductivity type, the semiconductor pillar including a first region opposing each of the first conducting films, and a second region provided between the first regions with respect to the first direction, the second region having a resistance different from a resistance of the first region; and a second insulating film provided between the semiconductor pillar and the first conducting film.Type: GrantFiled: March 12, 2010Date of Patent: September 24, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi, Ryouhei Kirisawa, Junya Matsunami, Tomoko Fujiwara
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Publication number: 20130228850Abstract: A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.Type: ApplicationFiled: April 5, 2013Publication date: September 5, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Hiroyasu TANAKA, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Yoshiaki Fukuzumi, Yosuke Komori, Megumi Ishiduki, Tomoko Fujiwara, Junya Matsunami, Ryouhei Kirisawa
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Patent number: 8440528Abstract: A nonvolatile semiconductor memory device includes: forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes; forming a through-hole extending in a stacking direction in the stacked body; etching a portion of the interlayer insulating film facing the through-hole via the through-hole to remove the portion; forming a removed portion; forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed; forming a floating gate electrode in the portion in which the interlayer insulating films are removed; forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and burying a semiconductor pillar in the through-hole.Type: GrantFiled: December 15, 2009Date of Patent: May 14, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Masaru Kidoh, Tomoko Fujiwara, Yosuke Komori, Megumi Ishiduki, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Ryota Katsumata, Ryouhei Kirisawa, Junya Matsunami, Hideaki Aochi
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Patent number: 8436414Abstract: A nonvolatile semiconductor memory device includes: a semiconductor substrate; a stacked body provided on the semiconductor substrate, the stacked body having electrode films and insulating films being alternately stacked; a first and second semiconductor pillars; and a first and second charge storage layers. The first and second semiconductor pillars are provided inside a through hole penetrating through the stacked body in a stacking direction of the stacked body. The through hole has a cross section of an oblate circle, when cutting in a direction perpendicular to the stacking direction. The first and second semiconductor pillars face each other in a major axis direction of the first oblate circle. The first and second semiconductor pillars extend in the stacking direction. The first and second charge storage layers are provided between the electrode film and the first and second semiconductor pillars, respectively.Type: GrantFiled: February 16, 2010Date of Patent: May 7, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Yoshiaki Fukuzumi, Yosuke Komori, Megumi Ishiduki, Tomoko Fujiwara, Junya Matsunami, Ryouhei Kirisawa
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Patent number: 8436415Abstract: A memory string comprises: a first semiconductor layer including a columnar portion extending in a stacking direction on a substrate; a first charge storage layer surrounding the columnar portion; and a plurality of first conductive layers stacked on the substrate so as to surround the first charge storage layer. A select transistor comprises: a second semiconductor layer in contact with an upper surface of the columnar portion and extending in the stacking direction; a second charge storage layer surrounding the second semiconductor layer; and a second conductive layer deposited above the first conductive layer to surround the second charge storage layer. The second charge storage layer is formed from a layer downward of the second conductive layer to an upper end vicinity of the second conductive layer, and is not formed in a layer upward of the upper end vicinity.Type: GrantFiled: March 15, 2010Date of Patent: May 7, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kidoh, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Publication number: 20130109157Abstract: A non-volatile semiconductor storage device includes a plurality of memory strings each having a plurality of electrically rewritable memory cells connected in series. Each of the memory strings comprising: a first semiconductor layer including a columnar portion extending in a vertical direction with respect to a substrate; a plurality of first conductive layers formed to surround side surfaces of the columnar portions via insulation layers, and formed at a certain pitch in the vertical direction, the first conductive layers functioning as floating gates of the memory cells; and a plurality of second conductive layers formed to surround the first conductive layers via insulation layers, and functioning as control electrodes of the memory cells. Each of the first conductive layers has a length in the vertical direction that is shorter than a length in the vertical direction of each of the second conductive layers.Type: ApplicationFiled: December 21, 2012Publication date: May 2, 2013Inventors: Masaru KITO, Yoshiaki FUKUZUMI, Masaru KIDOH, Megumi ISHIDUKI, Yosuke KOMORI, Hiroyasu TANAKA, Ryota KATSUMATA, Hideaki AOCHI
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Patent number: 8426976Abstract: A non-volatile semiconductor storage device has a plurality of memory strings with a plurality of electrically rewritable memory cells connected in series. Each of the memory strings includes: a columnar semiconductor layer extending in a direction perpendicular to a substrate; a plurality of conductive layers formed at a sidewall of the columnar semiconductor layer via memory layers; and interlayer insulation layers formed above of below the conductive layers. A sidewall of the conductive layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes larger at lower position thereof than at upper position thereof. While, a sidewall of the interlayer insulation layers facing the columnar semiconductor layer is formed to be inclined such that the distance thereof from a central axis of the columnar semiconductor layer becomes smaller at lower position thereof than at upper position thereof.Type: GrantFiled: February 25, 2009Date of Patent: April 23, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Megumi Ishiduki, Hideaki Aochi, Ryota Katsumata, Hiroyasu Tanaka, Masaru Kidoh, Masaru Kito, Yoshiaki Fukuzumi, Yosuke Komori, Yasuyuki Matsuoka
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Publication number: 20130075742Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including a plurality of electrode layers and a plurality of insulating layers, which are alternately stacked, and diffusion suppressing layers each provided between each of the plurality of electrode layers and each of the plurality of insulating layers; and a memory film provided on a side wall of a hole penetrating the stacked body in a stacking direction. Each of the plurality of electrode layers is a first semiconductor layer containing a first impurity element. The diffusion suppressing layer is a second semiconductor layer containing a second impurity element which is different from the first impurity element. The diffusion suppressing layer is a film having an effect of suppressing diffusion of the first impurity element.Type: ApplicationFiled: March 19, 2012Publication date: March 28, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Tomo OHSAWA, Yosuke KOMORI
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Patent number: 8372720Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: GrantFiled: December 9, 2008Date of Patent: February 12, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi