Patents by Inventor Yosuke Komori
Yosuke Komori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8178917Abstract: A non-volatile semiconductor storage device includes a first layer and a second layer. The first layer includes: a plurality of first conductive layers extending in parallel to a substrate and laminated in a direction perpendicular to the substrate; a first insulation layer formed on an upper layer of the plurality of first conductive layers; a first semiconductor layer formed to penetrate the plurality of first conductive layers; and a charge accumulation layer formed between the first conductive layers and the first semiconductor layer. Respective ends of the first conductive layers are formed in a stepwise manner in relation to each other in a first direction.Type: GrantFiled: March 20, 2009Date of Patent: May 15, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Hideaki Aochi, Megumi Ishiduki, Yasuyuki Matsuoka
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Patent number: 8178919Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including electrode films alternately stacked with inter-electrode insulating films; first and second semiconductor pillars piercing the stacked structural unit; a connection portion semiconductor layer electrically connect the first and second semiconductor pillars; a connection portion conductive layer provided to oppose the connection portion semiconductor layer; a memory layer and an inner insulating film provided between the first and semiconductor pillars and each of the electrode films, and between the connection portion conductive layer and the connection portion semiconductor layer; an outer insulating film provided between the memory layer and each of the electrode films; and a connection portion outer insulating film provided between the memory layer and the connection portion conductive layer. The connection portion outer insulating film has a film thickness thicker than a film thickness of the outer insulating film.Type: GrantFiled: March 19, 2010Date of Patent: May 15, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tomoko Fujiwara, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Patent number: 8169826Abstract: A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having one end thereof connected to the first line; and a second line commonly connected to the other end of a plurality of the switch circuits. The switch circuit controls electrical connection between the second line and the first line.Type: GrantFiled: March 18, 2010Date of Patent: May 1, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tomoo Hishida, Yoshihisa Iwata, Megumi Ishiduki, Ryota Katsumata, Yoshiaki Fukuzumi, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Patent number: 8154068Abstract: Each of memory strings comprising: a first semiconductor layer having a pair of columnar portions extending in a vertical direction to a substrate and a joining portion formed to join lower ends of the pair of columnar portions; an electric charge accumulation layer formed to surround a side surface of the first semiconductor layer; and a first conductive layer formed to surround a side surface of the electric charge accumulation layer. The columnar portions are aligned at a first pitch in a first direction orthogonal to the vertical direction, and arranged in a staggered pattern at a second pitch in a second direction orthogonal to the vertical and first directions. The first conductive layers are configured to be arranged at the first pitch in the first direction, and extend to curve in a wave-like fashion in the second direction along the staggered-pattern arrangement.Type: GrantFiled: December 28, 2009Date of Patent: April 10, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Katsumata, Hideaki Aochi, Masaru Kito, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Masaru Kidoh, Yoshiaki Fukuzumi
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Patent number: 8148769Abstract: A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells.Type: GrantFiled: August 3, 2009Date of Patent: April 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi
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Patent number: 8138489Abstract: A non-volatile semiconductor storage device includes a plurality of memory element groups, each of the memory element groups having a plurality of memory elements, each of the memory elements having a resistance-change element and a Schottky diode connected in series. Each of the memory element groups includes: a first columnar layer extending in a lamination direction; a first insulation layer formed on a side surface of the first columnar layer and functioning as the resistance-change element; and a first conductive layer formed to surround the first columnar layer via the first insulation layer. The first conductive layer is formed of metal. The first columnar layer is formed of a semiconductor having such a impurity concentration that the first conductive layer and the semiconductor configure the Schottky diode.Type: GrantFiled: September 18, 2009Date of Patent: March 20, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Masaru Kidoh, Ryota Katsumata, Masaru Kito, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi, Yoshiaki Fukuzumi
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Publication number: 20120064683Abstract: A multilayer body is formed by alternately stacking electrode films serving as control gates and dielectric films in a direction orthogonal to an upper surface of a silicon substrate. Trenches extending in the word line direction are formed in the multilayer body and a memory film is formed on an inner surface of the trench. Subsequently, a silicon body is buried inside the trench, and a charge storage film and the silicon body are divided in the word line direction to form silicon pillars. This simplifies the configuration of memory cells in the bit line direction, and hence can shorten the arrangement pitch of the silicon pillars, decreasing the area per memory cell.Type: ApplicationFiled: November 21, 2011Publication date: March 15, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Megumi ISHIDUKI, Ryota KATSUMATA, Masaru KIDOH, Hiroyasu TANAKA, Yosuke KOMORI, Masaru KITO, Yoshiaki FUKUZUMI, Hideaki AOCHI
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Patent number: 8120961Abstract: A stacked body with a plurality of dielectric films and electrode films alternately stacked therein is provided. The electrode film is divided into a plurality of control gate electrodes extending in one direction. The stacked body is provided with a U-pillar penetrating through the select gate electrodes and the control gate electrodes, having one end connected to a source line, and having the other end connected to a bit line. Moreover, a different potential is applied to uppermost one of the control gate electrodes than that applied to the other control gate electrodes.Type: GrantFiled: November 2, 2009Date of Patent: February 21, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
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Patent number: 8089120Abstract: A semiconductor memory device includes: a semiconductor substrate; a stacked body with a plurality of conductive layers and a plurality of dielectric layers alternately stacked, the stacked body being provided on the semiconductor substrate; a semiconductor layer provided inside a hole formed through the stacked body, the semiconductor layer extending in stacking direction of the conductive layers and the dielectric layers; and a charge storage layer provided between the conductive layers and the semiconductor layer.Type: GrantFiled: September 18, 2009Date of Patent: January 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Masaru Kidoh, Ryota Katsumata, Masaru Kito, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi, Yoshiaki Fukuzumi
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Patent number: 8084807Abstract: A multilayer body is formed by alternately stacking electrode films serving as control gates and dielectric films in a direction orthogonal to an upper surface of a silicon substrate. Trenches extending in the word line direction are formed in the multilayer body and a memory film is formed on an inner surface of the trench. Subsequently, a silicon body is buried inside the trench, and a charge storage film and the silicon body are divided in the word line direction to form silicon pillars. This simplifies the configuration of memory cells in the bit line direction, and hence can shorten the arrangement pitch of the silicon pillars, decreasing the area per memory cell.Type: GrantFiled: August 5, 2009Date of Patent: December 27, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Megumi Ishiduki, Ryota Katsumata, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Masaru Kito, Yoshiaki Fukuzumi, Hideaki Aochi
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Patent number: 8048798Abstract: A method for manufacturing a nonvolatile semiconductor storage device, including: forming a first conductive layer so that it is sandwiched in an up-down direction by first insulating layers; forming a first hole so that it penetrates the first insulating layers and the first conductive layer; forming a first side wall insulating layer on a side wall facing the first hole; forming a sacrificing layer so that the sacrificing layer infills the first hole; forming a second conductive layer on an upper layer of the sacrificing layer so that the second conductive layer is sandwiched by the second insulating layer in an up-down direction; forming a second hole on a position which matches with the first hole so that the second hole penetrates the second insulating layer and the second conductive layer; forming a second side wall insulating layer on a side wall facing the second hole; removing the sacrificing layer after the formation of the second side wall insulating layer; and forming a semiconductor layer so thatType: GrantFiled: February 20, 2009Date of Patent: November 1, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kidoh, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Yasuyuki Matsuoka
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Patent number: 8017993Abstract: A nonvolatile semiconductor memory device includes: a stacked body with a plurality of insulating films and electrode films alternately stacked therein, through which a through hole extending in the stacking direction is formed; a semiconductor pillar buried inside the through hole; and a charge storage layer located on both sides of each of the electrode films in the stacking direction and insulated from the electrode film and the semiconductor pillar.Type: GrantFiled: March 17, 2009Date of Patent: September 13, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Hideaki Aochi
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Publication number: 20110215394Abstract: According to one embodiment, a semiconductor memory device includes a base, a stacked body, a memory film, a channel body, a contact plug, a global bit line, and a plurality of local bit lines. The base has a substrate and a peripheral circuit formed on the substrate. The stacked body has a plurality of conductive layers and insulating layers stacked alternately above the base. The memory film includes a charge storage film provided on an inner wall of a memory hole formed in a stacking direction of the stacked body. The channel body is provided inside the memory film in the memory hole. The contact plug is provided by piercing the stacked body. The global bit line is provided between the peripheral circuit and the stacked body and connected to a lower end portion of the contact plug. The plurality of local bit lines are provided above the stacked body and divided in an extending direction of the plurality of local bit lines.Type: ApplicationFiled: June 11, 2010Publication date: September 8, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yosuke Komori, Masaru Kidoh, Ryota Katsumata
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Patent number: 8013383Abstract: A nonvolatile semiconductor storage device has a plurality of memory strings in which a plurality of electrically rewritable memory cells are connected in series. The memory string has a columnar semiconductor layer extending in a direction perpendicular to a substrate; a conductive layer formed so as to sandwich a charge storing layer in cooperation with the columnar semiconductor layer; and a metal layer formed so as to be in contact with the top face of the conductive layer.Type: GrantFiled: February 20, 2009Date of Patent: September 6, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kidoh, Masaru Kito, Ryota Katsumata, Yoshiaki Fukuzumi, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi, Akihiro Nitayama, Hitoshi Ito, Yasuyuki Matsuoka
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Patent number: 8008710Abstract: A memory string has a semiconductor layer with a joining portion that is formed to join a plurality of columnar portions extending in a vertical direction with respect to a substrate and lower ends of the plurality of columnar portions. First conductive layers are formed in a laminated fashion to surround side surfaces of the columnar portions and an electric charge storage layer, and function as control electrodes of memory cells. A second conductive layer is formed around the plurality of columnar portions via a gate insulation film, and functions as control electrodes of selection transistors. Bit lines are formed to be connected to the plurality of columnar portions, respectively, with a second direction orthogonal to a first direction taken as a longitudinal direction.Type: GrantFiled: July 10, 2009Date of Patent: August 30, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi
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Patent number: 7982261Abstract: A nonvolatile semiconductor memory device includes a first stacked body on a silicon substrate, and a second stacked body is provided thereon. The first stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a first portion of a through-hole extending in a stacking direction is formed. The second stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a second portion of the through-hole is formed. A memory film is formed on an inner face of the through-hole, and a silicon pillar is buried in an interior of the through-hole. A central axis of the second portion of the through-hole is shifted from a central axis of the first portion, and a lower end of the second portion is positioned lower than an upper portion of the first portion.Type: GrantFiled: September 21, 2009Date of Patent: July 19, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kidoh, Hiroyasu Tanaka, Ryota Katsumata, Masaru Kito, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi, Yoshiaki Fukuzumi
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Patent number: 7969789Abstract: In a nonvolatile semiconductor memory device having n (n is an integer of two or more) electrode films stacked and having charge storage layers provided above and below each of the electrode films, when data “0” is written by injecting electrons into the charge storage layer on a source line side of a memory cell of the number k (k is an integer of 1 to (n?1)) as counted from an end on a bit line side in a selected semiconductor pillar, positive program potential is given to the electrode film of the number 1 to k as counted from the bit line side, and 0 V is given to the electrode film of the number (k+1) to n, therewith positive potential is given to the bit line and 0 V is given to the source line.Type: GrantFiled: August 5, 2009Date of Patent: June 28, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Yosuke Komori, Hideaki Aochi
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Publication number: 20110127597Abstract: A nonvolatile semiconductor memory device with charge storage layers with high reliability is provided. A plurality of insulating films and a plurality of electrode films 14 are alternately stacked on a substrate 11, and a plurality of selection gate electrodes 17 extending in the X direction and a plurality of bit lines BL extending in the Y direction are provided thereon. U-shaped silicon members 33 are provided, each of which is constituted by a plurality of silicon pillars 31 passing through the electrode films 14 and the selection gate electrode 17, whose upper ends are connected to the bit lines BL, and a connective member 32 connecting lower parts of one pair of the silicon pillars 31 disposed in diagonal positions. The electrode film 14 of each layer is divided for the respective selection gate electrodes 17.Type: ApplicationFiled: July 1, 2009Publication date: June 2, 2011Inventors: Yoshiaki Fukuzumi, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Masaru Kito, Ryota Katsumata, Masaru Kidoh
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Publication number: 20110103149Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array and a control circuit. The memory cell array includes a stacked body, a through-hole, a semiconductor pillar, and a charge storage film. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. The through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in the through-hole. The charge storage film is provided between the electrode films and the semiconductor pillar. Memory cells are formed at each intersection between the electrode films and the semiconductor pillar.Type: ApplicationFiled: August 5, 2010Publication date: May 5, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ryota KATSUMATA, Hideaki Aochi, Hiroyasu Tanaka, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Publication number: 20110103153Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.Type: ApplicationFiled: August 5, 2010Publication date: May 5, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Ryota KATSUMATA, Hideaki Aochi, Hiroyasu Tanaka, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota