Patents by Inventor Yosuke Shimamune

Yosuke Shimamune has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9865734
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: January 9, 2018
    Assignee: SOCIONEXT INC.
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Publication number: 20170117412
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Application
    Filed: December 13, 2016
    Publication date: April 27, 2017
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Patent number: 9577098
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: February 21, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Publication number: 20160308053
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Application
    Filed: June 22, 2016
    Publication date: October 20, 2016
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Patent number: 9401427
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: July 26, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Patent number: 9178034
    Abstract: A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: November 3, 2015
    Assignee: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masahiro Fukuda, Eiji Yoshida, Yosuke Shimamune
  • Publication number: 20150295086
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Application
    Filed: June 23, 2015
    Publication date: October 15, 2015
    Applicant: SOCIONEXT INC.
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Patent number: 9112027
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: August 18, 2015
    Assignee: SOCIONEXT INC.
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Publication number: 20140361340
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Application
    Filed: August 26, 2014
    Publication date: December 11, 2014
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Patent number: 8853673
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: October 7, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Publication number: 20140193960
    Abstract: A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.
    Type: Application
    Filed: March 12, 2014
    Publication date: July 10, 2014
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masahiro Fukuda, Eiji Yoshida, Yosuke Shimamune
  • Patent number: 8709898
    Abstract: A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: April 29, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masahiro Fukuda, Eiji Yoshida, Yosuke Shimamune
  • Patent number: 8586438
    Abstract: Recesses are formed in a pMOS region 2, and a SiGe layer is then formed so as to cover a bottom surface and a side surface of each of the recesses. Next, a SiGe layer containing Ge at a lower content than that in the SiGe layer is formed on each of the SiGe layers.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: November 19, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Naoyoshi Tamura, Yosuke Shimamune, Hirotaka Maekawa
  • Publication number: 20130248930
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Application
    Filed: May 15, 2013
    Publication date: September 26, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Patent number: 8518785
    Abstract: A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: August 27, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yosuke Shimamune, Masahiro Fukuda, Young Suk Kim, Akira Katakami, Akiyoshi Hatada, Naoyoshi Tamura, Hiroyuki Ohta
  • Publication number: 20130210207
    Abstract: A method includes: etching a silicon substrate except for a silicon substrate portion on which a channel region is to be formed to form first and second trenches respectively at a first side and a second side of the silicon substrate portion; filling the first and second trenches by epitaxially growing a semiconductor layer having etching selectivity against silicon and further a silicon layer; removing the semiconductor layer selectivity by a selective etching process to form voids underneath the silicon layer respectively at the first side and the second side of the substrate portion; burying the voids at least partially with a buried insulation film; forming a gate insulation film and a gate electrode on the silicon substrate portion; and forming a source region in the silicon layer at the first side of the silicon substrate portion and a drain region at the second side of the silicon substrate portion.
    Type: Application
    Filed: July 18, 2012
    Publication date: August 15, 2013
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Masahiro Fukuda, Eiji Yoshida, Yosuke Shimamune
  • Patent number: 8497191
    Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: July 30, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masahiro Fukuda, Yosuke Shimamune, Masaaki Koizuka, Katsuaki Ookoshi
  • Patent number: 8466450
    Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.
    Type: Grant
    Filed: July 29, 2010
    Date of Patent: June 18, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
  • Patent number: 8455324
    Abstract: A method of manufacturing a semiconductor device which includes forming a gate insulating film and a gate electrode over a semiconductor substrate, forming a first recess in the first semiconductor substrate on both sides of the gate electrode by dry etching, forming a second recess by removing a bottom and sidewalls of the first recess by wet etching, and forming a semiconductor layer in the second recess.
    Type: Grant
    Filed: October 2, 2009
    Date of Patent: June 4, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masahiro Fukuda, Yosuke Shimamune
  • Patent number: 8455325
    Abstract: A method of manufacturing a semiconductor device which includes forming a gate insulating film and a gate electrode over a semiconductor substrate, forming a first recess in the first semiconductor substrate on both sides of the gate electrode by dry etching, forming a second recess by removing a bottom and sidewalls of the first recess by wet etching, and forming a semiconductor layer in the second recess.
    Type: Grant
    Filed: January 10, 2012
    Date of Patent: June 4, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masahiro Fukuda, Yosuke Shimamune