Patents by Inventor Yosuke Shimamune
Yosuke Shimamune has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110014765Abstract: A method of manufacturing a semiconductor device including forming a gate insulating film and a gate electrode over a Si substrate; forming a recess in the Si substrate at both sides of the gate electrode; forming a first Si layer including Ge in the recess; forming an interlayer over the first Si layer; forming a second Si layer including Ge over the interlayer; wherein the interlayer is composed of Si or Si including Ge, and a Ge concentration of the interlayer is less than a Ge concentration of the first Si layer and a Ge concentration of the second Si layer.Type: ApplicationFiled: August 13, 2010Publication date: January 20, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Masahiro Fukuda, Yosuke Shimamune
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Publication number: 20100301350Abstract: Recesses are formed in a pMOS region 2, and a SiGe layer is then formed so as to cover a bottom surface and a side surface of each of the recesses. Next, a SiGe layer containing Ge at a lower content than that in the SiGe layer is formed on each of the SiGe layers.Type: ApplicationFiled: June 29, 2010Publication date: December 2, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Naoyoshi Tamura, Yosuke Shimamune, Hirotaka Maekawa
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Publication number: 20100301394Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: ApplicationFiled: July 29, 2010Publication date: December 2, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Patent number: 7816766Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate in correspondence to a channel region via a gate insulation film, and source and drain regions of p-type formed in the silicon substrate at respective outer sides of sidewall insulation films on the gate electrode, a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films epitaxially to the silicon substrate so as to be enclosed respectively by the source and drain regions, each of the SiGe mixed crystal regions being grown to a level above a level of a gate insulation film interface between the gate insulation film and the silicon substrate, wherein there is provided a compressive stress film at respective top surfaces of the SiGe mixed crystal regions.Type: GrantFiled: May 18, 2005Date of Patent: October 19, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Naoyoshi Tamura, Yosuke Shimamune, Akiyoshi Hatada, Akira Katakami, Masashi Shima
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Patent number: 7807524Abstract: A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and a p-channel field effect transistor formed in the semiconductor substrate and having p-type source/drain regions made of a third semiconductor material different from the first semiconductor material, wherein the second and third semiconductor materials are different materials. The semiconductor device having n- and p-channel transistors has improved performance by utilizing stress.Type: GrantFiled: May 4, 2009Date of Patent: October 5, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Young Suk Kim, Yosuke Shimamune
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Patent number: 7791064Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: April 18, 2005Date of Patent: September 7, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Publication number: 20100210083Abstract: A method of manufacturing a semiconductor device includes forming a first cap film over gate electrodes formed in a first active region and a second active region, etching the first cap film over the first active region, forming a second cap film over the gate electrodes formed in the first active region and the second active region, etching the second cap film over the first active region, etching the first active region using the gate electrodes to form concave portions in the first active region, and embedding a semiconductor material in the concave portions.Type: ApplicationFiled: January 20, 2010Publication date: August 19, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Masahiro Fukuda, Yosuke Shimamune, Yuka Kase
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Publication number: 20100129971Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.Type: ApplicationFiled: February 2, 2010Publication date: May 27, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hiroyuki Ohta, Takashi Sakuma, Yosuke Shimamune, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
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Publication number: 20100105184Abstract: A method of manufacturing a semiconductor device which includes forming a gate insulating film and a gate electrode over a semiconductor substrate, forming a first recess in the first semiconductor substrate on both sides of the gate electrode by dry etching, forming a second recess by removing a bottom and sidewalls of the first recess by wet etching, and forming a semiconductor layer in the second recess.Type: ApplicationFiled: October 2, 2009Publication date: April 29, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Masahiro Fukuda, Yosuke Shimamune
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Patent number: 7683362Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.Type: GrantFiled: June 21, 2006Date of Patent: March 23, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Hiroyuki Ohta, Takashi Sakuma, Yosuke Shimamune, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
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Patent number: 7679147Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.Type: GrantFiled: August 28, 2008Date of Patent: March 16, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Masahiro Fukuda, Yosuke Shimamune, Masaaki Koizuka, Katsuaki Ookoshi
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Patent number: 7667227Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: GrantFiled: January 16, 2009Date of Patent: February 23, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Publication number: 20100015774Abstract: A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.Type: ApplicationFiled: September 22, 2009Publication date: January 21, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Yosuke SHIMAMUNE, Masahiro Fukuda, Young Suk Kim, Akira Katakami, Akiyoshi Hatada, Naoyoshi Tamura, Hiroyuki Ohta
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Patent number: 7626215Abstract: A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.Type: GrantFiled: November 28, 2006Date of Patent: December 1, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Yosuke Shimamune, Masahiro Fukuda, Young Suk Kim, Akira Katakami, Akiyoshi Hatada, Naoyoshi Tamura, Hiroyuki Ohta
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Publication number: 20090280612Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.Type: ApplicationFiled: July 17, 2009Publication date: November 12, 2009Applicant: Fujitsu Microelectronics LimitedInventors: Yosuke Shimamune, Hiroyuki Ohta, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
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Publication number: 20090215240Abstract: A semiconductor device has: a semiconductor substrate made of a first semiconductor material; an n-channel field effect transistor formed in the semiconductor substrate and having n-type source/drain regions made of a second semiconductor material different from the first semiconductor material; and a p-channel field effect transistor formed in the semiconductor substrate and having p-type source/drain regions made of a third semiconductor material different from the first semiconductor material, wherein the second and third semiconductor materials are different materials. The semiconductor device having n- and p-channel transistors has improved performance by utilizing stress.Type: ApplicationFiled: May 4, 2009Publication date: August 27, 2009Applicant: FUJITSU LIMITEDInventors: Young Suk KIM, Yosuke Shimamune
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Patent number: 7579617Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.Type: GrantFiled: September 20, 2005Date of Patent: August 25, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Yosuke Shimamune, Hiroyuki Ohta, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
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Publication number: 20090176343Abstract: A p-channel MOS transistor includes a gate electrode formed on a silicon substrate in correspondence to a channel region therein via a gate insulation film, the gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, and source and drain regions of p-type are formed in the substrate at respective outer sides of the sidewall insulation films, wherein each of the source and drain regions encloses a polycrystal region of p-type accumulating therein a compressive stress.Type: ApplicationFiled: March 3, 2009Publication date: July 9, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Masashi Shima, Yosuke Shimamune, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
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Publication number: 20090134381Abstract: A semiconductor device includes a gate electrode formed on a silicon substrate via a gate insulation film in correspondence to a channel region, source and drain regions of a p-type diffusion region formed in the silicon substrate at respective outer sides of sidewall insulation films of the gate electrode, and a pair of SiGe mixed crystal regions formed in the silicon substrate at respective outer sides of. the sidewall insulation films in epitaxial relationship to the silicon substrate, the SiGe mixed crystal regions being defined by respective sidewall surfaces facing with each other, wherein, in each of the SiGe mixed crystal regions, the sidewall surface is defined by a plurality of facets forming respective, mutually different angles with respect to a principal surface of the silicon substrate.Type: ApplicationFiled: January 16, 2009Publication date: May 28, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Yosuke Shimamune, Akira Katakami, Akiyoshi Hatada, Masashi Shima, Naoyoshi Tamura
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Publication number: 20090117715Abstract: A semiconductor device in which selectivity in epitaxial growth is improved. There is provided a semiconductor device comprising a gate electrode formed over an Si substrate, which is a semiconductor substrate, with a gate insulating film therebetween and an insulating layer formed over sides of the gate electrode and containing a halogen element. With this semiconductor device, a silicon nitride film which contains the halogen element is formed over the sides of the gate electrode when an SiGe layer is formed over the Si substrate. Therefore, the SiGe layer epitaxial-grows over the Si substrate with high selectivity. As a result, an OFF-state leakage current which flows between, for example, the gate electrode and source/drain regions is suppressed and a manufacturing process suitable for actual mass production is established.Type: ApplicationFiled: October 14, 2008Publication date: May 7, 2009Applicant: FUJITSU LIMITEDInventors: Masahiro Fukuda, Yosuke Shimamune, Masaaki Koizuka, Katsuaki Ookoshi