Patents by Inventor Yosuke Ueno
Yosuke Ueno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9602748Abstract: There is provided a solid-state imaging device including an imaging unit including a plurality of image sensors, and an analog to digital (AD) conversion unit including a plurality of AD converters arranged in a row direction, each AD converter performing AD conversion of an electrical signal output by the image sensor. Each of the AD converters includes a comparator having a differential pair at an input stage, the differential pair including a first transistor and a second transistor, the first and second transistors are each divided into an equal number of a plurality of division transistors, and an arrangement pattern of the plurality of division transistors constituting the comparator in a predetermined column and an arrangement pattern of the plurality of division transistors constituting the comparator in an adjacent column adjacent to the predetermined column are different from each other.Type: GrantFiled: September 6, 2016Date of Patent: March 21, 2017Assignee: Sony CorporationInventors: Yosuke Ueno, Natsuko Seino, Kenichi Takamiya
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Publication number: 20170053957Abstract: An imaging element comprises a photoelectric conversion unit formed in a pixel region and configured to convert light into electrical charge. Further, the imaging element includes a transistor formed in the pixel region and configured to transfer electric charge from the photoelectric conversion unit. The photoelectric conversion unit of the imaging element may be connected to a well of the pixel region, where the well of the pixel region has a negative potential.Type: ApplicationFiled: February 17, 2015Publication date: February 23, 2017Inventors: Yosuke UENO, Yusuke IKEDA, Shizunori MATSUMOTO, Tsutomu HARUTA, Rei YOSHIKAWA
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Patent number: 9549136Abstract: There is provided a solid-state imaging device including an imaging unit including a plurality of image sensors, and an analog to digital (AD) conversion unit including a plurality of AD converters arranged in a row direction, each AD converter performing AD conversion of an electrical signal output by the image sensor. Each of the AD converters includes a comparator having a differential pair at an input stage, the differential pair including a first transistor and a second transistor, the first and second transistors are each divided into an equal number of a plurality of division transistors, and an arrangement pattern of the plurality of division transistors constituting the comparator in a predetermined column and an arrangement pattern of the plurality of division transistors constituting the comparator in an adjacent column adjacent to the predetermined column are different from each other.Type: GrantFiled: June 2, 2015Date of Patent: January 17, 2017Assignee: Sony CorporationInventors: Yosuke Ueno, Natsuko Seino, Kenichi Takamiya
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Publication number: 20170006243Abstract: A semiconductor apparatus, a solid-state image sensing apparatus, and a camera system capable of reducing interference between signals transmitted through adjacent via holes, preventing an increase in the number of the via holes, reducing the area of a chip having sensors thereon and the number of mounting steps thereof. First and second chips are bonded together to form a laminated structure, a wiring between the first chip and the second chip being connected through via holes, the first chip transmitting signals obtained by time-discretizing analog signals generated by respective sensors to the second chip through the corresponding via holes, the second chip sampling the signals transmitted from the first chip through the via holes at a timing different from a timing at which the signals are sampled by the first chip and quantizing the sampled signals to obtain digital signals.Type: ApplicationFiled: September 13, 2016Publication date: January 5, 2017Inventors: Toshiaki Nagai, Ken Koseki, Yosuke Ueno, Atsushi Suzuki
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Publication number: 20160373681Abstract: There is provided a solid-state imaging device including an imaging unit including a plurality of image sensors, and an analog to digital (AD) conversion unit including a plurality of AD converters arranged in a row direction, each AD converter performing AD conversion of an electrical signal output by the image sensor. Each of the AD converters includes a comparator having a differential pair at an input stage, the differential pair including a first transistor and a second transistor, the first and second transistors are each divided into an equal number of a plurality of division transistors, and an arrangement pattern of the plurality of division transistors constituting the comparator in a predetermined column and an arrangement pattern of the plurality of division transistors constituting the comparator in an adjacent column adjacent to the predetermined column are different from each other.Type: ApplicationFiled: September 6, 2016Publication date: December 22, 2016Inventors: Yosuke Ueno, Natsuko Seino, Kenichi Takamiya
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Publication number: 20160360130Abstract: There is provided a solid-state image sensor including a pixel array unit in which pixels are arrayed, the pixel including a photodiode converting an optical signal into an electrical signal, and a readout unit which reads out an analog image signal from the pixel to a signal line and processes the read out analog pixel signal in a unit of column. The readout unit includes a ?? modulator which has a function to convert the analog pixel signal in to a digital signal, and an amplifier which is arranged on an input side of the ?? modulator and amplifies the analog pixel signal read out to the signal line using a set gain to input the signal to the ?? modulator.Type: ApplicationFiled: August 16, 2016Publication date: December 8, 2016Inventors: Hayato Wakabayashi, Yosuke Ueno
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Patent number: 9509933Abstract: A semiconductor apparatus, a solid-state image sensing apparatus, and a camera system capable of reducing interference between signals transmitted through adjacent via holes, preventing an increase in the number of the via holes, reducing the area of a chip having sensors thereon and the number of mounting steps thereof. First and second chips are bonded together to form a laminated structure, a wiring between the first chip and the second chip being connected through via holes, the first chip transmitting signals obtained by time-discretizing analog signals generated by respective sensors to the second chip through the corresponding via holes, the second chip sampling the signals transmitted from the first chip through the via holes at a timing different from a timing at which the signals are sampled by the first chip and quantizing the sampled signals to obtain digital signals.Type: GrantFiled: March 23, 2016Date of Patent: November 29, 2016Assignee: Sony CorporationInventors: Toshiaki Nagai, Ken Koseki, Yosuke Ueno, Atsushi Suzuki
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Patent number: 9451189Abstract: There is provided a solid-state image sensor including a pixel array unit in which pixels are arrayed, the pixel including a photodiode converting an optical signal into an electrical signal, and a readout unit which reads out an analog image signal from the pixel to a signal line and processes the read out analog pixel signal in a unit of column. The readout unit includes a ?? modulator which has a function to convert the analog pixel signal in to a digital signal, and an amplifier which is arranged on an input side of the ?? modulator and amplifies the analog pixel signal read out to the signal line using a set gain to input the signal to the ?? modulator.Type: GrantFiled: October 11, 2012Date of Patent: September 20, 2016Assignee: Sony CorporationInventors: Hayato Wakabayashi, Yosuke Ueno
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Publication number: 20160227145Abstract: A semiconductor apparatus, a solid-state image sensing apparatus, and a camera system capable of reducing interference between signals transmitted through adjacent via holes, preventing an increase in the number of the via holes, reducing the area of a chip having sensors thereon and the number of mounting steps thereof. First and second chips are bonded together to form a laminated structure, a wiring between the first chip and the second chip being connected through via holes, the first chip transmitting signals obtained by time-discretizing analog signals generated by respective sensors to the second chip through the corresponding via holes, the second chip sampling the signals transmitted from the first chip through the via holes at a timing different from a timing at which the signals are sampled by the first chip and quantizing the sampled signals to obtain digital signals.Type: ApplicationFiled: March 23, 2016Publication date: August 4, 2016Inventors: Toshiaki Nagai, Ken Koseki, Yosuke Ueno, Atsushi Suzuki
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Patent number: 9407846Abstract: An analog-to-digital conversion device includes a plurality of counting period supply units that supply a period of length according to a voltage of an analog signal inputted into each counting period supply unit based on the voltage of the analog signal as a counting period, a plurality of counter circuits which are connected to a common power supply and which perform a counting operation that counts a count value in the counting period different from each other and generate a digital signal indicating the count value, and a plurality of compensation circuits which are connected to the power supply and which operate so that the greater the number of counter circuits that stop the counting operation among the plurality of counter circuits, the greater the number of the compensation circuits that operate.Type: GrantFiled: November 14, 2014Date of Patent: August 2, 2016Assignee: Sony CorporationInventors: Yasunori Tsukuda, Takashi Moue, Yosuke Ueno
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Patent number: 9350929Abstract: A semiconductor apparatus, a solid-state image sensing apparatus, and a camera system capable of reducing interference between signals transmitted through adjacent via holes, preventing an increase in the number of the via holes, reducing the area of a chip having sensors thereon and the number of mounting steps thereof. A first chip and a second chip are bonded together to form a laminated structure, a wiring between the first chip and the second chip being connected through via holes, the first chip transmitting signals obtained by time-discretizing analog signals generated by respective sensors to the second chip through the corresponding via holes, the second chip having a function of sampling the signals transmitted from the first chip through the via holes at a timing different from a timing at which the signals are sampled by the first chip and a function of quantizing the sampled signals to obtain digital signals.Type: GrantFiled: October 10, 2012Date of Patent: May 24, 2016Assignee: SONY CORPORATIONInventors: Toshiaki Nagai, Ken Koseki, Yosuke Ueno, Atsushi Suzuki
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Patent number: 9350527Abstract: There is provided a reception unit, including: a transition detection section configured to detect a transition of an input data signal; an oscillation section configured to generate a clock signal and vary a phase of the clock signal based on a result of detection made by the transition detection section, the clock signal having a frequency in accordance with a first control signal; a first sampling section configured to sample the input data signal based on the clock signal and thereby generate an output data signal; and a control section configured to generate the first control signal based on the input data signal, the output data signal, and the clock signal.Type: GrantFiled: March 24, 2015Date of Patent: May 24, 2016Assignee: SONY CORPORATIONInventors: Takashi Masuda, Yosuke Ueno, Zhiwei Zhou, Kenichi Maruko, Jeremy Chatwin
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Publication number: 20150371591Abstract: A display panel includes a plurality of first unit pixels (Pix) each including: a first data input terminals (PDIN); a first data output terminal (PDOUT); a display element (48); and a first waveform shaping section (42, 22), in which the display element (48) is configured to perform display based on first data (PD) inputted to the first data input terminal (PDIN), and the first waveform shaping section (42, 44) is provided on a signal path from the first data input terminal (PDIN) to the first data output terminal (PDOUT).Type: ApplicationFiled: December 20, 2013Publication date: December 24, 2015Inventors: Hideyuki SUZUKI, Toshiyuki MIYAUCHI, Yosuke UENO, Yoshifumi MIYAJIMA, Masayuki HATTORI, Kazukuni TAKANOHASHI, Haruo TOGASHI, Tamotsu IKEDA, Hiizu OOTORII, Sachiya TANAKA
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Publication number: 20150271430Abstract: There is provided a solid-state imaging device including an imaging unit including a plurality of image sensors, and an analog to digital (AD) conversion unit including a plurality of AD converters arranged in a row direction, each AD converter performing AD conversion of an electrical signal output by the image sensor. Each of the AD converters includes a comparator having a differential pair at an input stage, the differential pair including a first transistor and a second transistor, the first and second transistors are each divided into an equal number of a plurality of division transistors, and an arrangement pattern of the plurality of division transistors constituting the comparator in a predetermined column and an arrangement pattern of the plurality of division transistors constituting the comparator in an adjacent column adjacent to the predetermined column are different from each other.Type: ApplicationFiled: June 2, 2015Publication date: September 24, 2015Inventors: Yosuke Ueno, Natsuko Seino, Kenichi Takamiya
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Patent number: 9071783Abstract: There is provided a solid-state imaging device including an imaging unit including a plurality of image sensors, and an analog to digital (AD) conversion unit including a plurality of AD converters arranged in a row direction, each AD converter performing AD conversion of an electrical signal output by the image sensor. Each of the AD converters includes a comparator having a differential pair at an input stage, the differential pair including a first transistor and a second transistor, the first and second transistors are each divided into an equal number of a plurality of division transistors, and an arrangement pattern of the plurality of division transistors constituting the comparator in a predetermined column and an arrangement pattern of the plurality of division transistors constituting the comparator in an adjacent column adjacent to the predetermined column are different from each other.Type: GrantFiled: June 26, 2013Date of Patent: June 30, 2015Assignee: SONY CORPORATIONInventors: Yosuke Ueno, Natsuko Seino, Kenichi Takamiya
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Patent number: 9065607Abstract: A clock data recovery circuit includes: an oscillator that outputs a clock signal; a phase comparator that outputs a signal corresponding to a phase difference between an input reception data signal and the clock signal; a divider that outputs a feedback clock signal; a first variable delay circuit that outputs a delay data signal; a second variable delay circuit that outputs a delay feedback clock signal; a frequency phase comparator that outputs a signal corresponding to a frequency difference and a phase difference between the delay data signal and the delay feedback clock signal; a lock detector that outputs a determination signal indicating whether or not the frequency difference and the phase difference are within a predetermined range; and a multiplexer that receives the determination signal and select a signal of the phase comparator and a signal of the frequency phase comparator.Type: GrantFiled: November 20, 2013Date of Patent: June 23, 2015Assignee: Sony CorporationInventors: Kenichi Maruko, Yosuke Ueno
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Publication number: 20150171884Abstract: An analog-to-digital conversion device includes a plurality of counting period supply units that supply a period of length according to a voltage of an analog signal inputted into each counting period supply unit based on the voltage of the analog signal as a counting period, a plurality of counter circuits which are connected to a common power supply and which perform a counting operation that counts a count value in the counting period different from each other and generate a digital signal indicating the count value, and a plurality of compensation circuits which are connected to the power supply and which operate so that the greater the number of counter circuits that stop the counting operation among the plurality of counter circuits, the greater the number of the compensation circuits that operate.Type: ApplicationFiled: November 14, 2014Publication date: June 18, 2015Inventors: Yasunori Tsukuda, Takashi Moue, Yosuke Ueno
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Publication number: 20140293103Abstract: There is provided a solid-state image sensor including a pixel array unit in which pixels are arrayed, the pixel including a photodiode converting an optical signal into an electrical signal, and a readout unit which reads out an analog image signal from the pixel to a signal line and processes the read out analog pixel signal in a unit of column. The readout unit includes a ?? modulator which has a function to convert the analog pixel signal in to a digital signal, and an amplifier which is arranged on an input side of the ?? modulator and amplifies the analog pixel signal read out to the signal line using a set gain to input the signal to the ?? modulator.Type: ApplicationFiled: October 11, 2012Publication date: October 2, 2014Inventors: Hayato Wakabayashi, Yosuke Ueno
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Publication number: 20140232916Abstract: A semiconductor apparatus, a solid-state image sensing apparatus, and a camera system capable of reducing interference between signals transmitted through adjacent via holes, preventing an increase in the number of the via holes, reducing the area of a chip having sensors thereon and the number of mounting steps thereof. A first chip and a second chip are bonded together to form a laminated structure, a wiring between the first chip and the second chip being connected through via holes, the first chip transmitting signals obtained by time-discretizing analog signals generated by respective sensors to the second chip through the corresponding via holes, the second chip having a function of sampling the signals transmitted from the first chip through the via holes at a timing different from a timing at which the signals are sampled by the first chip and a function of quantizing the sampled signals to obtain digital signals.Type: ApplicationFiled: October 10, 2012Publication date: August 21, 2014Inventors: Toshiaki Nagai, Ken Koseki, Yosuke Ueno, Atsushi Suzuki
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Patent number: 8767106Abstract: Disclosed herein is a comparator including: a first input sampling capacitance; a second input sampling capacitance; an output node; a transconductance (Gm) amplifier as a differential comparator section configured to receive a slope signal, a signal level of the slope signal changing with a slope, at one input terminal of the Gm amplifier via the first input sampling capacitance, and receive an input signal at another input terminal of the Gm amplifier via the second input sampling capacitance, and subject the slope signal and the input signal to comparing operation; and an isolator configured to hold a voltage of an output section of the Gm amplifier constant, the isolator being disposed between the output section of the Gm amplifier and the output node.Type: GrantFiled: October 16, 2012Date of Patent: July 1, 2014Assignee: Sony CorporationInventor: Yosuke Ueno