Patents by Inventor Yotaro Goto

Yotaro Goto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10566367
    Abstract: The performances of a semiconductor device are improved. A semiconductor device has a transfer transistor and a photodiode. The photodiode has an n type semiconductor region, an n+ type semiconductor region, and a second p type semiconductor region surrounded by a first p type semiconductor region of an interpixel isolation region. The n+ type semiconductor region is formed on the main surface side of the semiconductor substrate, and the n type semiconductor region is formed under the n+ type semiconductor region via the second p type semiconductor region. In the channel length direction of the transfer transistor, in the n type semiconductor region, an n?? type semiconductor region having a lower impurity density than that of the n type semiconductor region is arranged, to improve the transfer efficiency of electric charges accumulated in the photodiode.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: February 18, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yotaro Goto, Takeshi Kamino, Fumitoshi Takahashi
  • Patent number: 10566373
    Abstract: In a solid state image sensor having two semiconductor substrates or more laminated longitudinally, electrical connection between the semiconductor substrates is made by a fine plug. An insulating film covering a first rear surface of a semiconductor substrate having a light receiving element, and an interlayer insulating film covering a second main surface of a semiconductor substrate mounting a semiconductor element are joined to each other. In its joint surface, a plug penetrating the insulating film and a lug embedded in a connection hole in an upper surface of the interlayer insulating film are joined, and the light receiving element and the semiconductor element are electrically connected through the plugs.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: February 18, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Yotaro Goto, Tatsuya Kunikiyo, Hidenori Sato
  • Patent number: 10504950
    Abstract: In order to improve the performance of a solid-state imaging device, the solid-state imaging device has a pixel including a photoelectric conversion unit and a transfer transistor, and fluorine is introduced to a gate electrode and a drain region (extension region and n+-type semiconductor region) of the transfer transistor included in the pixel.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: December 10, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Fumitoshi Takahashi, Yotaro Goto
  • Patent number: 10297624
    Abstract: A reduction is achieved in the power consumption of a solid-state imaging element including a photoelectric conversion element which converts incident light to charge and a transistor which converts the charge obtained in the photoelectric conversion element to voltage. A photodiode and a charge read transistor which are included in a pixel in the CMOS solid-state imaging element are provided in a semiconductor substrate, while an amplification transistor included in the foregoing pixel is provided in a semiconductor layer provided over the semiconductor substrate via a buried insulating layer. In the semiconductor substrate located in a buried insulating layer region, a p+-type back-gate semiconductor region for controlling a threshold voltage of the amplification transistor is provided.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: May 21, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuya Kunikiyo, Hidenori Sato, Yotaro Goto, Fumitoshi Takahashi
  • Publication number: 20180366508
    Abstract: In a solid state image sensor having two semiconductor substrates or more laminated longitudinally, electrical connection between the semiconductor substrates is made by a fine plug. An insulating film covering a first rear surface of a semiconductor substrate having a light receiving element, and an interlayer insulating film covering a second main surface of a semiconductor substrate mounting a semiconductor element are joined to each other. In its joint surface, a plug penetrating the insulating film and a lug embedded in a connection hole in an upper surface of the interlayer insulating film are joined, and the light receiving element and the semiconductor element are electrically connected through the plugs.
    Type: Application
    Filed: May 17, 2018
    Publication date: December 20, 2018
    Inventors: Yotaro GOTO, Tatsuya KUNIKIYO, Hidenori SATO
  • Publication number: 20180358394
    Abstract: In order to improve the performance of a solid-state imaging device, the solid-state imaging device has a pixel including a photoelectric conversion unit and a transfer transistor, and fluorine is introduced to a gate electrode and a drain region (extension region and n+-type semiconductor region) of the transfer transistor included in the pixel.
    Type: Application
    Filed: March 16, 2018
    Publication date: December 13, 2018
    Inventors: Takeshi KAMINO, Fumitoshi TAKAHASHI, Yotaro GOTO
  • Publication number: 20180358393
    Abstract: In a solid-state imaging element having two or more photodiodes stacked in a vertical direction in each of pixels, electrons are prevented from moving between the respective photodiodes of the pixels adjacent to each other. The solid-state imaging element is formed by joining together a back surface of a first semiconductor wafer including one of the photodiodes and a wiring layer and a back surface of a second semiconductor wafer including another of the photodiodes and a wiring layer. By forming a first isolation region extending through a first semiconductor substrate forming the first semiconductor wafer and a second isolation region extending through a second semiconductor substrate forming the second semiconductor wafer, the photodiodes of one of the pixels are isolated from another of the pixels.
    Type: Application
    Filed: March 27, 2018
    Publication date: December 13, 2018
    Inventors: Hidenori SATO, Tatsuya KUNIKIYO, Yotaro GOTO
  • Publication number: 20180350861
    Abstract: A reduction is achieved in the power consumption of a solid-state imaging element including a photoelectric conversion element which converts incident light to charge and a transistor which converts the charge obtained in the photoelectric conversion element to voltage. A photodiode and a charge read transistor which are included in a pixel in the CMOS solid-state imaging element are provided in a semiconductor substrate, while an amplification transistor included in the foregoing pixel is provided in a semiconductor layer provided over the semiconductor substrate via a buried insulating layer. In the semiconductor substrate located in a buried insulating layer region, a p+-type back-gate semiconductor region for controlling a threshold voltage of the amplification transistor is provided.
    Type: Application
    Filed: March 23, 2018
    Publication date: December 6, 2018
    Inventors: Tatsuya KUNIKIYO, Hidenori SATO, Yotaro GOTO, Fumitoshi TAKAHASHI
  • Publication number: 20180315789
    Abstract: A semiconductor device which improves the dark current characteristics and transfer efficiency of a back-surface irradiation CMOS image sensor without an increase in the area of a semiconductor chip. In the CMOS image sensor, a pixel includes a transfer transistor and a photodiode with a pn junction. In plan view, a reflecting layer is formed over an n-type region which configures the photodiode, through an isolation insulating film. The reflecting layer extends over the gate electrode of the transfer transistor through a cap insulating film. A first layer signal wiring is electrically coupled to both the gate electrode and the reflecting layer through a contact hole made in an interlayer insulating film over the gate electrode, so the same potential is applied to the gate electrode and the reflecting layer.
    Type: Application
    Filed: February 15, 2018
    Publication date: November 1, 2018
    Inventors: Fumitoshi TAKAHASHI, Tatsuya KUNIKIYO, Hidenori SATO, Yotaro GOTO
  • Patent number: 10115751
    Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes a pixel including a first active region where a photodiode and a transfer transistor are formed and a second active region for supplying a grounding potential. Over a p-type semiconductor region in the second active region, a plug for supplying the grounding potential is disposed. In an n-type semiconductor region for a drain region of the transfer transistor formed in the first active region, a gettering element is introduced. However, in the p-type semiconductor region in the second active region, the gettering element is not introduced.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: October 30, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Yotaro Goto
  • Publication number: 20180308884
    Abstract: The performances of a semiconductor device are improved. A semiconductor device has a transfer transistor and a photodiode. The photodiode has an n type semiconductor region, an n+ type semiconductor region, and a second p type semiconductor region surrounded by a first p type semiconductor region of an interpixel isolation region. The n+ type semiconductor region is formed on the main surface side of the semiconductor substrate, and the n type semiconductor region is formed under the n+ type semiconductor region via the second p type semiconductor region. In the channel length direction of the transfer transistor, in the n type semiconductor region, an n?? type semiconductor region having a lower impurity density than that of the n type semiconductor region is arranged, to improve the transfer efficiency of electric charges accumulated in the photodiode.
    Type: Application
    Filed: February 20, 2018
    Publication date: October 25, 2018
    Inventors: Yotaro Goto, Takeshi Kamino, Fumitoshi Takahashi
  • Patent number: 10068941
    Abstract: An insulating liner layer has an extra-pixel removal region located outside a pixel region in a region of a vertical angle of at least one of four corners of the pixel region and having the insulating liner layer removed therefrom.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 4, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yotaro Goto
  • Patent number: 10056420
    Abstract: Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: August 21, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Yotaro Goto
  • Patent number: 10032820
    Abstract: An imaging device and a manufacturing method of the imaging device are provided, which can lower the level of a dark current in an optical black pixel without forming a new layer such as a hydrogen diffusion preventing film. Both of an insulating layer over a photodiode arranged over an effective pixel region and an insulating layer over a photodiode arranged over an OB pixel region include silicon nitride, are formed of the same layer, and are coupled with each other.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: July 24, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yotaro Goto
  • Publication number: 20170309668
    Abstract: An insulating liner layer has an extra-pixel removal region located outside a pixel region in a region of a vertical angle of at least one of four corners of the pixel region and having the insulating liner layer removed therefrom.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Inventor: Yotaro GOTO
  • Patent number: 9773830
    Abstract: An insulating liner layer has an extra-pixel removal region located outside a pixel region in a region of a vertical angle of at least one of four corners of the pixel region and having the insulating liner layer removed therefrom.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: September 26, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yotaro Goto
  • Publication number: 20170213862
    Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes a pixel including a first active region where a photodiode and a transfer transistor are formed and a second active region for supplying a grounding potential. Over a p-type semiconductor region in the second active region, a plug for supplying the grounding potential is disposed. In an n-type semiconductor region for a drain region of the transfer transistor formed in the first active region, a gettering element is introduced. However, in the p-type semiconductor region in the second active region, the gettering element is not introduced.
    Type: Application
    Filed: November 30, 2016
    Publication date: July 27, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Takeshi KAMINO, Yotaro GOTO
  • Publication number: 20170084658
    Abstract: Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Takeshi KAMINO, Yotaro GOTO
  • Publication number: 20170062497
    Abstract: An imaging device and a manufacturing method of the imaging device are provided, which can lower the level of a dark current in an optical black pixel without forming a new layer such as a hydrogen diffusion preventing film. Both of an insulating layer over a photodiode arranged over an effective pixel region and an insulating layer over a photodiode arranged over an OB pixel region include silicon nitride, are formed of the same layer, and are coupled with each other.
    Type: Application
    Filed: June 22, 2016
    Publication date: March 2, 2017
    Applicant: Renesas Electronics Corporation
    Inventor: Yotaro GOTO
  • Patent number: 9564466
    Abstract: Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: February 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Yotaro Goto