Patents by Inventor Yotaro Goto

Yotaro Goto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10068941
    Abstract: An insulating liner layer has an extra-pixel removal region located outside a pixel region in a region of a vertical angle of at least one of four corners of the pixel region and having the insulating liner layer removed therefrom.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 4, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yotaro Goto
  • Patent number: 10056420
    Abstract: Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: August 21, 2018
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Yotaro Goto
  • Patent number: 10032820
    Abstract: An imaging device and a manufacturing method of the imaging device are provided, which can lower the level of a dark current in an optical black pixel without forming a new layer such as a hydrogen diffusion preventing film. Both of an insulating layer over a photodiode arranged over an effective pixel region and an insulating layer over a photodiode arranged over an OB pixel region include silicon nitride, are formed of the same layer, and are coupled with each other.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: July 24, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Yotaro Goto
  • Publication number: 20170309668
    Abstract: An insulating liner layer has an extra-pixel removal region located outside a pixel region in a region of a vertical angle of at least one of four corners of the pixel region and having the insulating liner layer removed therefrom.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Inventor: Yotaro GOTO
  • Patent number: 9773830
    Abstract: An insulating liner layer has an extra-pixel removal region located outside a pixel region in a region of a vertical angle of at least one of four corners of the pixel region and having the insulating liner layer removed therefrom.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: September 26, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yotaro Goto
  • Publication number: 20170213862
    Abstract: An improvement is achieved in the performance of a semiconductor device. A semiconductor device includes a pixel including a first active region where a photodiode and a transfer transistor are formed and a second active region for supplying a grounding potential. Over a p-type semiconductor region in the second active region, a plug for supplying the grounding potential is disposed. In an n-type semiconductor region for a drain region of the transfer transistor formed in the first active region, a gettering element is introduced. However, in the p-type semiconductor region in the second active region, the gettering element is not introduced.
    Type: Application
    Filed: November 30, 2016
    Publication date: July 27, 2017
    Applicant: Renesas Electronics Corporation
    Inventors: Takeshi KAMINO, Yotaro GOTO
  • Publication number: 20170084658
    Abstract: Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region.
    Type: Application
    Filed: November 30, 2016
    Publication date: March 23, 2017
    Inventors: Takeshi KAMINO, Yotaro GOTO
  • Publication number: 20170062497
    Abstract: An imaging device and a manufacturing method of the imaging device are provided, which can lower the level of a dark current in an optical black pixel without forming a new layer such as a hydrogen diffusion preventing film. Both of an insulating layer over a photodiode arranged over an effective pixel region and an insulating layer over a photodiode arranged over an OB pixel region include silicon nitride, are formed of the same layer, and are coupled with each other.
    Type: Application
    Filed: June 22, 2016
    Publication date: March 2, 2017
    Applicant: Renesas Electronics Corporation
    Inventor: Yotaro GOTO
  • Patent number: 9564466
    Abstract: Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: February 7, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takeshi Kamino, Yotaro Goto
  • Patent number: 9553121
    Abstract: A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: January 24, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroaki Sekikawa, Hidenori Sato, Yotaro Goto, Takuya Maruyama, Masaaki Shinohara
  • Publication number: 20160233262
    Abstract: An insulating liner layer has an extra-pixel removal region located outside a pixel region in a region of a vertical angle of at least one of four corners of the pixel region and having the insulating liner layer removed therefrom.
    Type: Application
    Filed: February 5, 2016
    Publication date: August 11, 2016
    Inventor: Yotaro GOTO
  • Publication number: 20160064323
    Abstract: A connection portion connects a copper-based first wiring layer with a copper-based second wiring layer arranged on the upper side of a first diffusion barrier film. The first diffusion barrier film includes a first opening region formed in a semiconductor circuit region that is a partial region in a two-dimensional view and a second opening region formed as an opening region different from the first opening region in a two-dimensional view. The opening regions are formed in a region different from an opening region formed to allow the connection portion to pass through the first diffusion barrier film. A mark wiring layer is arranged immediately above the second opening region as the same layer as the second wiring layer. A second diffusion barrier film is arranged in contact with the upper surface of the mark wiring layer.
    Type: Application
    Filed: August 25, 2015
    Publication date: March 3, 2016
    Inventors: Hiroaki SEKIKAWA, Hidenori SATO, Yotaro GOTO, Takuya MARUYAMA, Masaaki SHINOHARA
  • Publication number: 20160043131
    Abstract: Provided is a semiconductor device with improved performance. The semiconductor device includes a photodiode having a charge storage layer (n-type semiconductor region) and a surface layer (p-type semiconductor region), and a transfer transistor having a gate electrode and a floating diffusion. The surface layer (p-type semiconductor region) of a second conductive type formed over the charge storage layer (n-type semiconductor region) of a first conductive type includes a first sub-region having a low impurity concentration, and a second sub-region having a high impurity concentration. The first sub-region is arranged closer to the floating diffusion than the second sub-region.
    Type: Application
    Filed: July 20, 2015
    Publication date: February 11, 2016
    Inventors: Takeshi Kamino, Yotaro Goto