Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

Abstract: The present invention provides a processor including a source generator, a request synchronization signal generator and an output circuit. The source generator is configured to generate image data of a frame. The request synchronization signal generator is configured to generate a request synchronization signal to an integrated circuit only after the source generator generates the image data of the frame completely, wherein the request synchronization signal is used to trigger the integrated circuit to send a synchronization signal to the processor. The output circuit is configured to send the image data of the frame to the integrated circuit only after receiving the synchronization signal generated from the integrated circuit in response to the request synchronization signal.

Abstract: The present invention provides a control method of a processor, wherein the control method comprises the steps of: transmitting image data of a first frame to an integrated circuit, wherein the first frame corresponds to a first frame rate; determining a second frame rate of a second frame next to the first frame; determining if a difference between the second frame rate and the first frame rate belongs to a large scale frame rate adjustment or a small scale frame rate adjustment; if the difference between the second frame rate and the first frame rate belongs to the large scale frame rate adjustment, using a first mode to transmit image data of the second frame; and if the difference between the second frame rate and the first frame rate belongs to the small scale frame rate adjustment, using a second mode to transmit image data of the second frame.

Abstract: A device generates blended frames, with each blended frame composed of multiple image layers and each image layer composed of multiple regions. The device includes display hardware. The display hardware retrieves a given image layer in a current frame from a memory. Based on at least content hints generated at the display hardware for the given image layer in the current frame, the display hardware makes a determination of whether to skip access to the memory for retrieving each region of each image layer in a next frame that is immediately after the current frame, and accesses the memory for the next frame according to the determination.

Abstract: A signal processing apparatus includes a first signal processing block and a second signal processing block. The first signal processing block is utilized for processing an input signal to generate a first target processing result, including a plurality of packets initially reproduced from the input signal, to an output port of the first signal processing circuit, where each of the packets contains a corresponding packet identifier (PID). The second signal processing block has an input port coupled to the output port of the first signal processing circuit, and is utilized for processing the first target processing result according to PIDs of the packets and accordingly generating a second target processing result. There is no buffer coupled between the output port of the first signal processing circuit and the input port of the second signal processing circuit.

Abstract: A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information and data length information which are derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.

Abstract: A method for setting the bandwidth of a multiple stream decrypting and decoding system includes at least the following steps: authenticating a multiple transport stream decryption card; sending a transport stream through the system; extracting program information from the transport stream; utilizing the program information to set a bandwidth limit to the system; and enabling the multiple transport stream decryption card.

Abstract: A dynamic polarity control method for driving an LCD is provided. Gray level information is obtained, which indicates gray levels of dots in an image to be displayed. The gray level information is applied to each of a plurality of polarity patterns to obtain a plurality of combined patterns, wherein each of the polarity patterns has an individual polarity distribution. The gray levels of each of the combined patterns are summed up. A final pattern is selected from the plurality of polarity patterns according to the summed results, to drive the LCD for displaying the image.

Abstract: A transport stream processing apparatus includes a demodulation module, a transport stream storage module, a multiplexer, and a conditional access system interface. The demodulation module is for demodulating an input signal to generate a first transport stream. The transport stream storage module is for storing a second transport stream. The multiplexer has an output port, a first input port for receiving the first transport stream, and a second input port for receiving the second transport stream. The multiplexer selectively couples the first input port or the second input port to the output port. The conditional access system interface is coupled to the output port of the multiplexer for coupling a conditional access module. The conditional access system interface transmits a transport stream outputted from the output port of the multiplexer to the conditional access module for signal processing when the conditional access module is coupled to the conditional access system interface.

Abstract: A transport stream processing system capable of recording and playing back a transport stream carrying a plurality of transport stream packets is provided, and includes: a first memory unit storing a plurality of sets of control words; a packet identifier filter acquiring a set of control words according to a packet identifier value of a transport stream packet and configuring an indicator to indicate whether the transport stream packet is for a recording or a playback operation; a second memory unit storing a plurality of data structures, wherein each data structure corresponds to an index number of each set of control words; and a processor determining whether the recording or playback operation for the transport stream packet is performed for the transport stream packet according to the indicator, retrieving a data structure according to the index number corresponding to the acquired set of control words and performing the operation accordingly.

Abstract: A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.

Abstract: A method for setting the bandwidth of a multiple stream decrypting and decoding system includes at least the following steps: authenticating a multiple transport stream decryption card; sending a transport stream through the system; extracting program information from the transport stream; utilizing the program information to set a bandwidth limit to the system; and enabling the multiple transport stream decryption card.

Abstract: A system for decrypting multiple transport streams is disclosed. The system includes: a Multiple Transport stream Multiplexer (M-Mux), for receiving at least a first transport stream and a second transport stream, and outputting a resultant transport stream; a multiple transport stream decryption card for decrypting the resultant transport stream to output a decrypted transport stream; a Source Multiplexer (S-Mux) for receiving the decrypted transport stream from the multiple transport stream decryption card and the resultant transport stream, and outputting a final resultant transport stream; and a Multiple Transport Stream Processor (M-Processor) for receiving the final resultant transport stream, and sending the final resultant transport stream to a corresponding framer.

Abstract: A dynamic polarity control method for driving an LCD is provided. Gray level information is obtained, which indicates gray levels of dots in an image to be displayed. The gray level information is applied to each of a plurality of polarity patterns to obtain a plurality of combined patterns, wherein each of the polarity patterns has an individual polarity distribution. The gray levels of each of the combined patterns are summed up. A final pattern is selected from the plurality of polarity patterns according to the summed results, to drive the LCD for displaying the image.

Abstract: A transport stream processing apparatus includes a demodulation module, a transport stream storage module, a multiplexer, and a conditional access system interface. The demodulation module is for demodulating an input signal to generate a first transport stream. The transport stream storage module is for storing a second transport stream. The multiplexer has an output port, a first input port for receiving the first transport stream, and a second input port for receiving the second transport stream. The multiplexer selectively couples the first input port or the second input port to the output port. The conditional access system interface is coupled to the output port of the multiplexer for coupling a conditional access module. The conditional access system interface transmits a transport stream outputted from the output port of the multiplexer to the conditional access module for signal processing when the conditional access module is coupled to the conditional access system interface.

Abstract: A transport stream processing system capable of recording and playing back a transport stream carrying a plurality of transport stream packets is provided, and includes: a first memory unit storing a plurality of sets of control words; a packet identifier filter acquiring a set of control words according to a packet identifier value of a transport stream packet and configuring an indicator to indicate whether the transport stream packet is for a recording or a playback operation; a second memory unit storing a plurality of data structures, wherein each data structure corresponds to an index number of each set of control words; and a processor determining whether the recording or playback operation for the transport stream packet is performed for the transport stream packet according to the indicator, retrieving a data structure according to the index number corresponding to the acquired set of control words and performing the operation accordingly.

Abstract: A combined digital TV decoding and optical recording system includes a transport stream demultiplexer to demultiplex at least one compressed multimedia stream from an MPEG transport stream having multiplexed compressed multimedia streams. A video encoder compresses a video stream to generate a second compressed video stream. A common system controller controls operations of the transport stream demultiplexer and the video encoder, and allocates portions of a memory to the transport stream demultiplexer and the MPEG video encoder based on respective memory requirements.

Abstract: A combined digital TV decoding and optical recording system includes a transport stream demultiplexer to demultiplex at least one compressed multimedia stream from an MPEG transport stream having multiplexed compressed multimedia streams. A video encoder compresses a video stream to generate a second compressed video stream. A common system controller controls operations of the transport stream demultiplexer and the video encoder, and allocates portions of a memory to the transport stream demultiplexer and the MPEG video encoder based on respective memory requirements.

Abstract: A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information and data length information which are derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.