Abstract: A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information and data length information which are derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.

Abstract: A signal processing apparatus includes a first signal processing block and a second signal processing block. The first signal processing block is utilized for processing an input signal to generate a first target processing result, including a plurality of packets initially reproduced from the input signal, to an output port of the first signal processing circuit, where each of the packets contains a corresponding packet identifier (PID). The second signal processing block has an input port coupled to the output port of the first signal processing circuit, and is utilized for processing the first target processing result according to PIDs of the packets and accordingly generating a second target processing result. There is no buffer coupled between the output port of the first signal processing circuit and the input port of the second signal processing circuit.

Abstract: A packet processing apparatus includes a packet identifying unit and a packet modifying unit. The packet identifying unit is utilized for receiving a plurality of packets and checking identification information derived from the received packets to identify first packets from the received packets. The packet modifying unit is coupled to the packet identifying unit, and is utilized for checking payloads of the first packets to identify second packets from the first packets, where each of the second packets has specific data included in a payload thereof, and for modifying at least the payload of each of the second packets.

Abstract: A validation system includes: a source agent for storing a plurality of test patterns; a drain agent for performing a validation operation according to a test result; and a device under test (DUT). The device under test includes: a first interface electrically connected to the source agent for communicating with the source agent and receiving the test patterns outputted from the source agent; a target system electrically connected to the first interface for processing the test patterns to generate a plurality of test results; and a second interface electrically connected to the target system and the drain agent for communicating with the drain agent and transferring the plurality of test results to the drain agent.

Abstract: A system for decrypting multiple transport streams is disclosed. The system includes: a Multiple Transport stream Multiplexer (M-Mux), for receiving at least a first transport stream and a second transport stream, and outputting a resultant transport stream; a multiple transport stream decryption card for decrypting the resultant transport stream to output a decrypted transport stream; a Source Multiplexer (S-Mux) for receiving the decrypted transport stream from the multiple transport stream decryption card and the resultant transport stream, and outputting a final resultant transport stream; and a Multiple Transport Stream Processor (M-Processor) for receiving the final resultant transport stream, and sending the final resultant transport stream to a corresponding framer.

Abstract: A validation system includes: a source agent for storing a plurality of test patterns; a drain agent for performing a validation operation according to a test result; and a device under test (DUT). The device under test includes: a first interface electrically connected to the source agent for communicating with the source agent and receiving the test patterns outputted from the source agent; a target system electrically connected to the first interface for processing the test patterns to generate a plurality of test results; and a second interface electrically connected to the target system and the drain agent for communicating with the drain agent and transferring the plurality of test results to the drain agent.

Abstract: A header information parsing and extracting method for a DTV decoding system is provided. A transport stream comprising a plurality of PES packets is received. At least one field of PES headers or headers within ES is selectively extracted from the transport stream to a programmable table. The access units are extracted from the PES packets to an elementary stream buffer. The fields in the programmable table are read to control an elementary stream decoding. The access units in the elementary stream buffer are read for the elementary stream decoding. The field to extract is selected by control signals, and the programmable table is accordingly established when the field is selected.

Abstract: The present invention relates to packet stream processing systems and methods for multiple cascaded units. Each unit has a packet rate compensator to maintain a time interval of packets output from the unit approximately the same as a corresponding input interval. A smooth real-time transmission and presentation can thus be ensured by keeping the same packet transmission rate with the original packet input rate for the packets. A signal synchronizer is located between asynchronous units or at the input of a unit receiving packets from an asynchronous source, to ensure reliable packet transmission across the units.

Abstract: An apparatus that includes a controller to regulate a rate of transfer of MPEG transport stream packets from a first storage device to a second storage device based on transfer rate control information derived from at least some of the MPEG transport stream packets. For example, the transfer rate control information may include time information, and the time information may include program clock references. In some examples, the first storage device can be a hard disk drive or a dynamic random access memory, and the second storage device can be a Blu-ray Disc recorder.

Abstract: A combined digital TV decoding and optical recording system includes a transport stream demultiplexer to demultiplex at least one compressed multimedia stream from an MPEG transport stream having multiplexed compressed multimedia streams. A video encoder compresses a video stream to generate a second compressed video stream. A common system controller controls operations of the transport stream demultiplexer and the video encoder, and allocates portions of a memory to the transport stream demultiplexer and the MPEG video encoder based on respective memory requirements.

Abstract: A digital television (DTV) system comprises a front-end circuit comprises a demodulator circuit for producing a non-decrypted transport stream signal; a back-end circuit for decoding transport stream data; an external memory coupled to the back-end circuit; an address bus and a data bus to which the external memory is coupled through a plurality of address and data pins; a cryptocard module coupled to the front-end circuit and the back-end circuit for decrypting transport stream data to produce a decrypted transport stream signal and for performing conditional access and security functions, the cryptocard module having address and data pins coupled to address and data pins of the external memory; and a switching means for providing either the non-decrypted transport stream signal produced by the front-end circuit or the decrypted transport stream signal produced by the cryptocard module to the back-end circuit.

Abstract: A digital television (DTV) system has a front-end circuit comprising a DTV demodulator and a back-end circuit. The back-end circuit includes a DTV demultiplexer, a cryptocard module controller, and an external memory controller. The DTV system also includes an external memory coupled to the back-end circuit, an address bus and a data bus to which the external memory is coupled through a plurality of address and data pins, and a cryptocard module coupled to the front-end circuit and the back-end circuit for performing conditional access and security functions, the cryptocard module having address and data pins coupled to address and data pins of the external memory.