Patents by Inventor You-Ru Lin
You-Ru Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240099147Abstract: In some embodiments, the present disclosure relates to a method in which a first set of one or more voltage pulses is applied to a piezoelectric device over a first time period. During the first time period, the method determines whether a performance parameter of the piezoelectric device has a first value that deviates from a reference value by more than a predetermined value. Based on whether the first value deviates from the reference value by more than the predetermined value, the method selectively applies a second set of one or more voltage pulses to the piezoelectric device over a second time period. The second time period is after the first time period and the second set of one or more voltage pulses differs in magnitude and/or polarity from the first set of one or more voltage pulses.Type: ApplicationFiled: November 20, 2023Publication date: March 21, 2024Inventors: Chi-Yuan Shih, Shih-Fen Huang, You-Ru Lin, Yan-Jie Liao
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Patent number: 11856862Abstract: In some embodiments, the present disclosure relates to a method in which a first set of one or more voltage pulses is applied to a piezoelectric device over a first time period. During the first time period, the method determines whether a performance parameter of the piezoelectric device has a first value that deviates from a reference value by more than a predetermined value. Based on whether the first value deviates from the reference value by more than the predetermined value, the method selectively applies a second set of one or more voltage pulses to the piezoelectric device over a second time period. The second time period is after the first time period and the second set of one or more voltage pulses differs in magnitude and/or polarity from the first set of one or more voltage pulses.Type: GrantFiled: July 27, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yuan Shih, Shih-Fen Huang, You-Ru Lin, Yan-Jie Liao
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Publication number: 20230386948Abstract: A semiconductor device and method of forming such a device includes a MEMS component including one or more MEMS pixels and having a MEMS membrane substrate and a MEMS sidewall. The semiconductor device includes an analog circuit component bonded to the MEMS component, and which includes at least one analog CMOS component within an analog circuit insulative layer, and an analog circuit component substrate. The semiconductor device includes an HPC component bonded to the analog circuit component substrate. The HPC component includes at least one HPC metal component disposed within an HPC insulative layer, at least one bond pad, at least one bond pad via connecting the at least one bond pad and the at least one HPC metal component, and an HPC substrate. Additionally, the semiconductor device includes a DTC component bonded to the HPC substrate, and which includes a DTC die disposed in a DTC substrate.Type: ApplicationFiled: May 25, 2022Publication date: November 30, 2023Inventors: You-Ru Lin, Sheng Kai Yeh, Jen-Yuan Chang, Chi-Yuan Shih, Chia-Ming Hung, Hsiang-Fu Chen, Shih-Fen Huang
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Patent number: 11730058Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.Type: GrantFiled: May 16, 2019Date of Patent: August 15, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Alexander Kalnitsky, Chun-Ren Cheng, Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yan-Jie Liao
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Publication number: 20230060423Abstract: The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.Type: ApplicationFiled: November 14, 2022Publication date: March 2, 2023Inventors: You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
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Publication number: 20220384709Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.Type: ApplicationFiled: August 5, 2022Publication date: December 1, 2022Inventors: Alexander Kalnitsky, Chun-Ren Cheng, Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yan-Jie Liao
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Publication number: 20220367564Abstract: In some embodiments, the present disclosure relates to a method in which a first set of one or more voltage pulses is applied to a piezoelectric device over a first time period. During the first time period, the method determines whether a performance parameter of the piezoelectric device has a first value that deviates from a reference value by more than a predetermined value. Based on whether the first value deviates from the reference value by more than the predetermined value, the method selectively applies a second set of one or more voltage pulses to the piezoelectric device over a second time period. The second time period is after the first time period and the second set of one or more voltage pulses differs in magnitude and/or polarity from the first set of one or more voltage pulses.Type: ApplicationFiled: July 27, 2022Publication date: November 17, 2022Inventors: Chi-Yuan Shih, Shih-Fen Huang, You-Ru Lin, Yan-Jie Liao
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Patent number: 11502186Abstract: The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.Type: GrantFiled: October 5, 2020Date of Patent: November 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
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Patent number: 11456330Abstract: In some embodiments, the present disclosure relates to a method for recovering degraded device performance of a piezoelectric device. The method includes operating the piezoelectric device in a performance mode by applying one or more voltage pulses to the piezoelectric device, and determining that a performance parameter of the piezoelectric device has a first value that has deviated from a reference value by more than a predetermined threshold value during a first time period. During a second time period, the method further includes applying a bipolar loop to the piezoelectric device, comprising positive and negative voltage biases. During a third time period, the method further includes operating the piezoelectric device in the performance mode, wherein the performance parameter has a second value. An absolute difference between the second value and the reference value is less than an absolute difference between the first value and the reference value.Type: GrantFiled: August 7, 2019Date of Patent: September 27, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yuan Shih, Shih-Fen Huang, You-Ru Lin, Yan-Jie Liao
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Patent number: 11289568Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.Type: GrantFiled: May 13, 2019Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Wen-Chuan Tai, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Anderson Lin, Fu-Chun Huang, Chun-Ren Cheng, Ivan Hua-Shu Wu, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
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INTEGRATION SCHEME FOR BREAKDOWN VOLTAGE ENHANCEMENT OF A PIEZOELECTRIC METAL-INSULATOR-METAL DEVICE
Publication number: 20210383972Abstract: Various embodiments of the present disclosure are directed towards an integrated chip including a dielectric structure sandwiched between a first electrode and a bottom electrode. A passivation layer overlies the second electrode and the dielectric structure. The passivation layer comprises a horizontal surface vertically below a top surface of the passivation layer. The horizontal surface is disposed above a top surface of the dielectric structure.Type: ApplicationFiled: August 25, 2021Publication date: December 9, 2021Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao -
Patent number: 11177368Abstract: Methods of semiconductor arrangement formation are provided. A method of forming the semiconductor arrangement includes forming a first nucleus on a substrate in a trench or between dielectric pillars on the substrate. Forming the first nucleus includes applying a first source material beam at a first angle relative to a top surface of the substrate and concurrently applying a second source material beam at a second angle relative to the top surface of the substrate. A first semiconductor column is formed from the first nucleus by rotating the substrate while applying the first source material beam and the second source material beam. Forming the first semiconductor column in the trench or between the dielectric pillars using the first source material beam and the second source material beam restricts the formation of the first semiconductor column to a single direction.Type: GrantFiled: April 15, 2019Date of Patent: November 16, 2021Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Wei-Chieh Chen, Hao-Hsiung Lin, Shu-Han Chen, You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
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Integration scheme for breakdown voltage enhancement of a piezoelectric metal-insulator-metal device
Patent number: 11107630Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.Type: GrantFiled: May 21, 2019Date of Patent: August 31, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao -
Patent number: 10957607Abstract: A method for manufacturing a semiconductor device is provided. A semiconductor substrate is received. The semiconductor substrate is patterned to form a plurality of protrusions spaced from one another, wherein the protrusion comprises a base section, and a seed section stacked on the base section. A plurality of first insulative structures are formed, covering sidewalls of the base sections and exposing sidewalls of the seed sections. A plurality of spacers are formed, covering the sidewalls of the seed sections. The first insulative structures are partially removed to partially expose the sidewalls of the base sections. The base sections exposed from the first insulative structures are removed. A plurality of second insulative structures are formed under the seed sections.Type: GrantFiled: December 27, 2019Date of Patent: March 23, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Sheng Yun, You-Ru Lin, Shao-Ming Yu
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Publication number: 20210043680Abstract: In some embodiments, the present disclosure relates to a method for recovering degraded device performance of a piezoelectric device. The method includes operating the piezoelectric device in a performance mode by applying one or more voltage pulses to the piezoelectric device, and determining that a performance parameter of the piezoelectric device has a first value that has deviated from a reference value by more than a predetermined threshold value during a first time period. During a second time period, the method further includes applying a bipolar loop to the piezoelectric device, comprising positive and negative voltage biases. During a third time period, the method further includes operating the piezoelectric device in the performance mode, wherein the performance parameter has a second value. An absolute difference between the second value and the reference value is less than an absolute difference between the first value and the reference value.Type: ApplicationFiled: August 7, 2019Publication date: February 11, 2021Inventors: Chi-Yuan Shih, Shih-Fen Huang, You-Ru Lin, Yan-Jie Liao
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Publication number: 20210036131Abstract: The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.Type: ApplicationFiled: October 5, 2020Publication date: February 4, 2021Inventors: You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
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Patent number: 10797162Abstract: The present disclosure provides a FinFET device. The FinFET device comprises a semiconductor substrate of a first semiconductor material; a fin structure of the first semiconductor material overlying the semiconductor substrate, wherein the fin structure has a top surface of a first crystal plane orientation; a diamond-like shape structure of a second semiconductor material disposed over the top surface of the fin structure, wherein the diamond-like shape structure has at least one surface of a second crystal plane orientation; a gate structure disposed over the diamond-like shape structure, wherein the gate structure separates a source region and a drain region; and a channel region defined in the diamond-like shape structure between the source and drain regions.Type: GrantFiled: December 13, 2018Date of Patent: October 6, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: You-Ru Lin, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
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Publication number: 20200144132Abstract: A method for manufacturing a semiconductor device is provided. A semiconductor substrate is received. The semiconductor substrate is patterned to form a plurality of protrusions spaced from one another, wherein the protrusion comprises a base section, and a seed section stacked on the base section. A plurality of first insulative structures are formed, covering sidewalls of the base sections and exposing sidewalls of the seed sections. A plurality of spacers are formed, covering the sidewalls of the seed sections. The first insulative structures are partially removed to partially expose the sidewalls of the base sections. The base sections exposed from the first insulative structures are removed. A plurality of second insulative structures are formed under the seed sections.Type: ApplicationFiled: December 27, 2019Publication date: May 7, 2020Inventors: WEI-SHENG YUN, YOU-RU LIN, SHAO-MING YU
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Publication number: 20200098517Abstract: Various embodiments of the present disclosure are directed towards a piezoelectric metal-insulator-metal (MIM) device including a piezoelectric structure between a top electrode and a bottom electrode. The piezoelectric layer includes a top region overlying a bottom region. Outer sidewalls of the bottom region extend past outer sidewalls of the top region. The outer sidewalls of the top region are aligned with outer sidewalls of the top electrode. The piezoelectric layer is configured to help limit delamination of the top electrode from the piezoelectric layer.Type: ApplicationFiled: May 21, 2019Publication date: March 26, 2020Inventors: Anderson Lin, Chun-Ren Cheng, Chi-Yuan Shih, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Fu-Chun Huang, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
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Publication number: 20200098969Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.Type: ApplicationFiled: May 16, 2019Publication date: March 26, 2020Inventors: Alexander Kalnitsky, Chun-Ren Cheng, Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yan-Jie Liao