Abstract: An embedded integrated circuit package system is provided forming a first conductive pattern on a first structure, connecting a first integrated circuit die on the first conductive pattern, forming a substrate forming encapsulation to cover the first integrated circuit die and the first conductive pattern, forming a channel in the substrate forming encapsulation, and applying a conductive material in the channel.

Abstract: A stacked integrated circuit package system is provided forming a lead and a die paddle from a lead frame, forming a first integrated circuit die having an interconnect provided thereon, placing a second integrated circuit die over the first integrated circuit die and the die paddle, connecting the second integrated circuit die and the lead, and encapsulating the first integrated circuit die and the second integrated circuit die with a portion of the lead and the interconnect exposed.

Abstract: The present invention provides a thermally enhanced power semiconductor package system comprising providing a power semiconductor die, forming an upper lead frame on the power semiconductor die and forming a lower lead frame below the power semiconductor die, wherein the upper lead frame and the lower lead frame are provided in an offset configuration relative to each other to provide two heat dissipation paths.

Abstract: An integrated circuit package system including a ribbon bond interconnect is provided, having a semiconductor device with at least one pad thereon. An external connection is provided. A heavy ribbon is provided and bonded to the external connection and to the pad on the semiconductor device.

Abstract: The present invention provides a stackable power semiconductor package system comprising forming a lower lead frame, having an upward bent source lead and an upward bent gate lead, mounting a power semiconductor device on the lower lead frame utilizing interconnect structures and forming an upper lead frame wherein the upper lead frame is on the power semiconductor device.

Abstract: An integrated circuit package system includes a conductive substrate. A heat sink and a plurality of leads are etched in the substrate to define a conductive film connecting the heat sink and the plurality of leads to maintain their spatial relationship. A die is attached to the heat sink and wire bonded to the plurality of leads. An encapsulant is formed over the die, the heat sink, and the plurality of leads. The conductive film is etched away to expose the encapsulant and the bottom surfaces of the heat sink and the plurality of leads. Wave soldering is used to form solder on at least the plurality of leads. Multiple heat sinks and hanging leads are provided.

Abstract: A substrate indexing system comprising aligning a substrate with an indexing system, drawing the substrate along a long axis of the indexing system, and engaging the substrate using a self-aligning resilient tensioner with a chamfered edge.

Abstract: A non-leaded integrated circuits package system is provided including etching differential height lead structures having inner leads at a paddle height, providing mold locks at the bending points of the differential height lead structures, etching an elevated paddle at a same height as the inner leads, mounting a first integrated circuit on the elevated paddle, and electrically connecting first electrical interconnects between the first integrated circuit and the inner leads.

Abstract: A semiconductor package system is provided including mounting a semiconductor chip to a substrate having a substrate opening. A first heat slug is attached to a first surface of the semiconductor chip at least partially encapsulating the semiconductor chip. A second heat slug is attached to the second surface of the semiconductor chip through the substrate opening.

Abstract: A semiconductor package system is provided including mounting a semiconductor chip to a substrate having a substrate opening. A first heat slug is attached to a first surface of the semiconductor chip at least partially encapsulating the semiconductor chip. A second heat slug is attached to the second surface of the semiconductor chip through the substrate opening.