Patents by Inventor Youichi Tobita
Youichi Tobita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978580Abstract: A first dimension of each of a first connection portion 12 and a second connection portion 14 in the direction in which a pair of side surfaces 2e and 2f face each other is smaller than an inner diameter W2 of a coil 8 in the direction and is larger than a width W1 of each of a plurality of coil conductors in the direction. A second dimension of each of the first connection portion 12 and the second connection portion 14 in the direction in which a pair of main surfaces 2c and 2d face each other is larger than a thickness H1 of each of the plurality of coil conductors in the direction and is smaller than a height H2 of the coil 8 in the direction.Type: GrantFiled: November 26, 2019Date of Patent: May 7, 2024Assignee: TDK CORPORATIONInventors: Kazuya Tobita, Yuto Shiga, Youichi Kazuta, Noriaki Hamachi
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Patent number: 10762865Abstract: A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals.Type: GrantFiled: December 30, 2016Date of Patent: September 1, 2020Assignee: MITSUBISHI ELECTRIC CORPORATIONInventor: Youichi Tobita
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Publication number: 20170110077Abstract: A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals.Type: ApplicationFiled: December 30, 2016Publication date: April 20, 2017Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Youichi TOBITA
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Patent number: 9336897Abstract: A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit.Type: GrantFiled: April 25, 2012Date of Patent: May 10, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Youichi Tobita, Isao Nojiri, Seiichiro Mori, Takashi Miyayama
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Patent number: 9280942Abstract: An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver.Type: GrantFiled: January 2, 2014Date of Patent: March 8, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventor: Youichi Tobita
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Patent number: 9147370Abstract: For an image display apparatus, cost reduction is enabled to prevent display errors while ensuring operational margin to prevent display errors even when the delay time of gate line driving signals is large. A source driver of a liquid-crystal display apparatus includes a data latch circuit for supplying display data to a decode circuit. A gate line inactivation transition detecting circuit detects inactivation of each of a plurality of gate lines and activates a detect signal for a certain period with that timing. The data latch circuit updates the held display data in response to activation of the detect signal.Type: GrantFiled: December 8, 2010Date of Patent: September 29, 2015Assignee: Mitsubishi Electric CorporationInventors: Youichi Tobita, Yoshifumi Doi, Hiroyuki Murai
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Patent number: 8913709Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).Type: GrantFiled: November 25, 2013Date of Patent: December 16, 2014Assignee: Mitsubishi Electric CorporationInventor: Youichi Tobita
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Patent number: 8816949Abstract: In a shift register circuit, a defective operation while an output signal is not outputted and a drive capability lowering while the output signal is outputted are prevented. A unit shift register comprises a first transistor for supplying a clock signal inputted to a first clock terminal to an output terminal, and the first transistor is driven by a drive circuit. A second transistor is connected between the gate of the first transistor and the output terminal and has a gate connected to the first clock terminal. The second transistor connects the gate of the first transistor to the output terminal based on the clock signal when the gate of the first transistor is at L (Low) level.Type: GrantFiled: June 10, 2013Date of Patent: August 26, 2014Assignee: Mitsubishi Electric CorporationInventor: Youichi Tobita
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Publication number: 20140117358Abstract: An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver.Type: ApplicationFiled: January 2, 2014Publication date: May 1, 2014Applicant: Mitsubishi Electric CorporationInventor: Youichi TOBITA
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Publication number: 20140079174Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).Type: ApplicationFiled: November 25, 2013Publication date: March 20, 2014Applicant: Mitsubishi Electric CorporationInventor: Youichi TOBITA
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Patent number: 8654057Abstract: An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver.Type: GrantFiled: April 15, 2013Date of Patent: February 18, 2014Assignee: Mitsubishi Electric CorporationInventor: Youichi Tobita
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Patent number: 8615066Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).Type: GrantFiled: July 16, 2013Date of Patent: December 24, 2013Assignee: Mitsubishi Electric CorporationInventor: Youichi Tobita
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Patent number: 8593204Abstract: In an amplitude conversion circuit that converts an input signal having a small amplitude into an output signal having a large amplitude, the input signal is supplied to a gate of a transistor that discharges an output terminal through a capacitance element. A charging/discharging circuit causes a gate voltage of the transistor to be substantially equal to a threshold voltage during an inactive period of the input signal.Type: GrantFiled: July 26, 2010Date of Patent: November 26, 2013Assignee: Mitsubishi Electric CorporationInventor: Youichi Tobita
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Publication number: 20130301793Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).Type: ApplicationFiled: July 16, 2013Publication date: November 14, 2013Applicant: Mitsubishi Electric CorporationInventor: Youichi TOBITA
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Patent number: 8571169Abstract: Provided are a bi-directional scanning type gate line driving circuit that does not require a dummy unit shift register and a method of driving the same. In a gate line driving circuit including a multi-stage shift register capable of bi-directional shifting, a start pulse is input to a unit shift register at a first stage and a unit shift register at the last stage of the multi-stage shift register. In forward shifting, a clock signal supplied to the unit shift register at the last stage is kept at a deactivation level during a period from a time at which an activation period of an output signal of the unit shift register at the last stage ends to a time at which the start pulse is activated during a subsequent frame period.Type: GrantFiled: February 8, 2011Date of Patent: October 29, 2013Assignee: Mitsubishi Electric CorporationInventor: Youichi Tobita
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Patent number: 8571170Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).Type: GrantFiled: December 18, 2012Date of Patent: October 29, 2013Assignee: Mitsubishi Electric CorporationInventor: Youichi Tobita
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Publication number: 20130272487Abstract: In a shift register circuit, a defective operation while an output signal is not outputted and a drive capability lowering while the output signal is outputted are prevented. A unit shift register comprises a first transistor for supplying a clock signal inputted to a first clock terminal to an output terminal, and the first transistor is driven by a drive circuit. A second transistor is connected between the gate of the first transistor and the output terminal and has a gate connected to the first clock terminal. The second transistor connects the gate of the first transistor to the output terminal based on the clock signal when the gate of the first transistor is at L (Low) level.Type: ApplicationFiled: June 10, 2013Publication date: October 17, 2013Inventor: Youichi TOBITA
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Patent number: 8493309Abstract: In a shift register circuit, a defective operation while an output signal is not outputted and a drive capability lowering while the output signal is outputted are prevented. A unit shift register comprises a first transistor for supplying a clock signal inputted to a first clock terminal to an output terminal, and the first transistor is driven by a drive circuit. A second transistor is connected between the gate of the first transistor and the output terminal and has a gate connected to the first clock terminal. The second transistor connects the gate of the first transistor to the output terminal based on the clock signal when the gate of the first transistor is at L (Low) level.Type: GrantFiled: April 7, 2011Date of Patent: July 23, 2013Assignee: Mitsubishi Electric CorporationInventor: Youichi Tobita
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Patent number: 8462098Abstract: An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver.Type: GrantFiled: February 12, 2010Date of Patent: June 11, 2013Assignee: Mitsubishi Electric CorporationInventor: Youichi Tobita
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Publication number: 20130108006Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).Type: ApplicationFiled: December 18, 2012Publication date: May 2, 2013Inventor: Youichi TOBITA