Patents by Inventor Youichi Tobita

Youichi Tobita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10650950
    Abstract: A laminated electronic component includes an element body and a pair of conductors. The element body is formed by laminating a plurality of element-body layers in a first direction. The pair of conductors is formed by laminating a plurality of conductor layers in the first direction. The pair of conductors is provided to the element body in such a way as to be separated from each other in a second direction orthogonal to the first direction. At a cross section orthogonal to the first direction, the pair of conductors has an uneven portion and the element body has an uneven portion engaged with the uneven portion of the pair of conductors.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: May 12, 2020
    Assignee: TDK CORPORATION
    Inventors: Shunji Aoki, Yuya Ishima, Hajime Kato, Yuto Shiga, Kazuya Tobita, Youichi Kazuta, Satoru Okamoto
  • Publication number: 20200098507
    Abstract: A multilayer coil component includes an element body including a plurality of laminated insulator layers, and a coil disposed in the element body. The coil includes a first coil conductor having a first inner diameter, a second coil conductor having a second inner diameter smaller than the first inner diameter, and a connection conductor connecting the first coil conductor and the second coil conductor. The second coil conductor is adjacent to the first coil conductor in a direction in which the plurality of insulator layers are laminated. The connection conductor has a shape along the first coil conductor and the second coil conductor.
    Type: Application
    Filed: September 19, 2019
    Publication date: March 26, 2020
    Applicant: TDK CORPORATION
    Inventors: Yuto SHIGA, Hajime KATO, Kazuya TOBITA, Youichi KAZUTA, Noriaki HAMACHI, Makoto YOSHINO
  • Publication number: 20200066431
    Abstract: An electronic component includes an element provided with a recess, a mounting conductor disposed in the recess, and an internal conductor disposed inside the element and connected to the mounting conductor. A first region includes a first surface. A second region includes a third surface connecting a second surface and the first surface. The second surface and the third surface overlap with the first surface as viewed in a direction in which the first surface and the second surface face each other. The internal conductor is connected to the second region away from a connection portion between the first surface and the third surface.
    Type: Application
    Filed: August 12, 2019
    Publication date: February 27, 2020
    Applicant: TDK CORPORATION
    Inventors: Yuto SHIGA, Hajime KATO, Kazuya TOBITA, Youichi KAZUTA, Noriaki HAMACHI, Makoto YOSHINO
  • Publication number: 20190348214
    Abstract: In a multilayer coil component 1, a coil 7 includes a first connection part 22a and a second connection part 26a, the first connection part 22a is connected to one end part of the coil 7, which part is placed on a side of one principal surface 2c, and is arranged in an identical dielectric layer 6 with a conductor 22 included in the one end part, the second connection part 26a is connected to the other end part of the coil 7, which part is placed on a side of the other principal surface 2d, and is arranged in an identical dielectric layer 6 with a conductor 26 included in the other end part, and recessed parts 8a and 8b and recessed parts 9a and 9b are respectively provided in the first terminal electrode 4 and the second terminal electrode 5 in the element body 2.
    Type: Application
    Filed: April 25, 2019
    Publication date: November 14, 2019
    Applicant: TDK CORPORATION
    Inventors: Kazuya TOBITA, Hajime KATO, Makoto YOSHINO, Youichi KAZUTA, Yuto SHIGA, Noriaki HAMACHI
  • Publication number: 20190333686
    Abstract: A multilayer coil component includes an element assembly that has a first surface and second surfaces and extending in a direction orthogonal to the first surface, and terminal electrodes that has first electrode parts extending in a direction orthogonal to the first surface along the second surfaces. At least a portion of the first electrode parts of the terminal electrodes is disposed inside the element assembly. The element assembly is present between imaginary lines extending in a direction parallel to the first surface toward the second surfaces from a position farthest from the first surface in a direction orthogonal to the first surface in the first electrode parts positioned inside the element assembly and the first surface.
    Type: Application
    Filed: April 23, 2019
    Publication date: October 31, 2019
    Applicant: TDK CORPORATION
    Inventors: Youichi KAZUTA, Hajime KATO, Makoto YOSHINO, Kazuya TOBITA, Yuto SHIGA, Noriaki HAMACHI
  • Publication number: 20190237239
    Abstract: A laminated coil component 1 includes an element body 2, a coil 8 disposed in the element body 2, and a first external electrode 4 and a second external electrode 5, and at least a part of the coil 8 is disposed in a first region A1 and a second region A2 when seen in a facing direction of the pair of side surfaces 2e and 2f, and the coil 8 is not disposed in a third region A3 and a fourth region A4 when seen in the facing direction of the pair of side surfaces 2e and 2f.
    Type: Application
    Filed: January 16, 2019
    Publication date: August 1, 2019
    Applicant: TDK CORPORATION
    Inventors: Hajime KATO, Satoru OKAMOTO, Masahiro KATO, Makoto YOSHINO, Kazuya TOBITA, Yuto SHIGA, Youichi KAZUTA, Noriaki HAMACHI
  • Publication number: 20170110077
    Abstract: A gate-line drive circuit is driven by three clock signals of different phases, and includes a plurality of cascade-connected unit shift registers. In a normal operation, activation periods of the three clock signals do not overlap one another. However, the two clock signals of them are simultaneously activated at the beginning of a frame period. A unit shift register of the first stage is adapted to activate an output signal in accordance with the simultaneous activation of the two clock signals.
    Type: Application
    Filed: December 30, 2016
    Publication date: April 20, 2017
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Youichi TOBITA
  • Patent number: 9336897
    Abstract: A shift register circuit comprises a first transistor connected between a clock terminal and an output terminal, a second transistor for charging a control electrode of the first transistor in response to activation of an output signal of the preceding stage, a third transistor for discharging the control electrode of the first transistor, an inverter using a control electrode of the third transistor as an output end, and a fourth transistor which discharges an input end of the inverter at power-off and is turned off after power-on. A fifth transistor which is a load element of the inverter charges the control electrode of the third transistor at power-on. It is thereby possible to initialize the respective levels of the nodes without any external initialization signal and prevent a decrease in the level change rate of the output signal in the shift register circuit.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: May 10, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Youichi Tobita, Isao Nojiri, Seiichiro Mori, Takashi Miyayama
  • Patent number: 9280942
    Abstract: An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: March 8, 2016
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventor: Youichi Tobita
  • Patent number: 9147370
    Abstract: For an image display apparatus, cost reduction is enabled to prevent display errors while ensuring operational margin to prevent display errors even when the delay time of gate line driving signals is large. A source driver of a liquid-crystal display apparatus includes a data latch circuit for supplying display data to a decode circuit. A gate line inactivation transition detecting circuit detects inactivation of each of a plurality of gate lines and activates a detect signal for a certain period with that timing. The data latch circuit updates the held display data in response to activation of the detect signal.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: September 29, 2015
    Assignee: Mitsubishi Electric Corporation
    Inventors: Youichi Tobita, Yoshifumi Doi, Hiroyuki Murai
  • Patent number: 8913709
    Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: December 16, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Youichi Tobita
  • Patent number: 8816949
    Abstract: In a shift register circuit, a defective operation while an output signal is not outputted and a drive capability lowering while the output signal is outputted are prevented. A unit shift register comprises a first transistor for supplying a clock signal inputted to a first clock terminal to an output terminal, and the first transistor is driven by a drive circuit. A second transistor is connected between the gate of the first transistor and the output terminal and has a gate connected to the first clock terminal. The second transistor connects the gate of the first transistor to the output terminal based on the clock signal when the gate of the first transistor is at L (Low) level.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: August 26, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Youichi Tobita
  • Publication number: 20140117358
    Abstract: An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver.
    Type: Application
    Filed: January 2, 2014
    Publication date: May 1, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventor: Youichi TOBITA
  • Publication number: 20140079174
    Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).
    Type: Application
    Filed: November 25, 2013
    Publication date: March 20, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventor: Youichi TOBITA
  • Patent number: 8654057
    Abstract: An electro-optical device is configured to be capable of using a region of a gate line drive circuit efficiently and preventing rising speed of a gate line selection signal from decreasing (rising delay), and a shift register circuit is composed of a single conductivity type transistor which is suitable for the device. The gate line drive circuit including an odd driver to drive odd rows of a plurality of gate lines, and an even driver to drive even rows thereof. Each unit shift register in the odd and even drivers receives a selection signal in the second previous row and activates its own selection signal two horizontal periods later. A start pulse of the even driver is delayed in phase by one horizontal period with respect to a start pulse of the odd driver.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: February 18, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventor: Youichi Tobita
  • Patent number: 8615066
    Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: December 24, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Youichi Tobita
  • Patent number: 8593204
    Abstract: In an amplitude conversion circuit that converts an input signal having a small amplitude into an output signal having a large amplitude, the input signal is supplied to a gate of a transistor that discharges an output terminal through a capacitance element. A charging/discharging circuit causes a gate voltage of the transistor to be substantially equal to a threshold voltage during an inactive period of the input signal.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: November 26, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Youichi Tobita
  • Publication number: 20130301793
    Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).
    Type: Application
    Filed: July 16, 2013
    Publication date: November 14, 2013
    Applicant: Mitsubishi Electric Corporation
    Inventor: Youichi TOBITA
  • Patent number: 8571170
    Abstract: An object is to enhance the driving capability and improve the operating speed of a unit shift register applicable to a scanning line driving circuit having a partial display function. A unit shift register forming a gate line driving circuit includes a first transistor that supplies a first clock signal to a first output terminal, a second transistor that supplies a second clock signal to a second output terminal, a third transistor that charges the gate of the first transistor in response to activation of a shift signal of the previous stage, and a fourth transistor connected between the gate of the first transistor and the gate of the second transistor. The first clock signal and the second clock signal have the same phase, and only the second clock signal is activated in a particular period (a display ineffective period).
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: October 29, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Youichi Tobita
  • Patent number: 8571169
    Abstract: Provided are a bi-directional scanning type gate line driving circuit that does not require a dummy unit shift register and a method of driving the same. In a gate line driving circuit including a multi-stage shift register capable of bi-directional shifting, a start pulse is input to a unit shift register at a first stage and a unit shift register at the last stage of the multi-stage shift register. In forward shifting, a clock signal supplied to the unit shift register at the last stage is kept at a deactivation level during a period from a time at which an activation period of an output signal of the unit shift register at the last stage ends to a time at which the start pulse is activated during a subsequent frame period.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: October 29, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventor: Youichi Tobita