Abstract: A dual-gate transistor formed of two transistors connected in series between a first power terminal and a first node is used as a charging circuit for charging a gate node (first node) of a transistor intended to pull up an output terminal of a unit shift register. The dual-gate transistor is configured such that the connection node (second node) between the two transistors constituting the dual-gate transistor is pulled down to the L level by the capacitive coupling between the gate and second node in accordance with the change of the gate from the H level to the L level.

Abstract: A shift register has an output stage formed by a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a ground. Third and fourth transistors are connected in series between the gate of the first transistor (first node) and the ground. A second node between the third and fourth transistors is connected to a power source via a fifth transistor. The fifth transistor has its gate connected to the first node. Accordingly, when the third and fourth transistors are turned off to raise the first node in level, the fifth transistor is turned on, whereby a predetermined voltage is applied to the second node.

Abstract: A unit shift register includes a first transistor for supplying an output terminal with a clock signal, and second and third transistors for discharging the output terminal, and further includes a fourth transistor having its gate connected to the gate node of the second transistor and discharging the gate node of the first transistor, and a fifth transistor having its gate connected to the gate node of the third transistor and discharging the gate node of the first transistor. Input of the clock signal is prohibited just after the change in level of first and second control signals for switching between the second and third transistors.

Abstract: A gradation potential generating circuit of a color liquid crystal display apparatus includes a first ladder resistor circuit having a relatively high resistance value and generating first to sixty-fourth gradation potentials by dividing a power supply voltage to apply them to first to sixty-fourth nodes, and a second ladder resistor circuit having a relatively low resistance value, activated during an initial predetermined period of a time period while a selected gradation potential is applied to a data line, and generating first to sixty-fourth gradation potentials by dividing the power supply voltage to apply them to first to sixty-fourth nodes, and 65 switches. Therefore, since the ladder resistor circuit having low resistance is activated in a pulsed manner, the data line can be charged/discharged at a high-speed with low current consumption.

Abstract: A shift register includes a first transistor connected between an output terminal and a first clock terminal, a second transistor connected between the output terminal and a first power terminal, and an inverter in which a first node to which the gate of the first transistor is connected serves as an input node and a second node to which the gate of the second transistor is connected serves as an output node. The inverter has third and fourth transistors connected in series between the second node and a first power terminal, both having their gates connected to the first node, a fifth transistor connected between the second node and a third power terminal having its gate connected to the third power terminal, and a sixth transistor connected between a fourth power terminal and a third node serving as a connection node between the third and fourth transistors. The sixth transistor has its gate connected to the second node.

Abstract: A shift register includes a first transistor supplying an output terminal with a clock signal input to a first clock terminal and a second transistor discharging the output terminal. Defining the gate node of the first transistor as a first node, and the gate node of the second transistor as a second node, the shift register includes an inverter circuit in which the first node serves as its input node and a capacitive element serves as a load, and a buffer circuit receiving the output from the inverter circuit and outputting a signal to the second node.

Abstract: A first transistor is arranged between a reference voltage node and a first node, and is connected at its gate to a second node. A second transistor is arranged between the second node and the reference voltage node, and is connected at its gate to the first node. Charges are supplied to the first and second nodes via capacitance elements receiving first and second control signals, respectively. Further, a third transistor is arranged between the second node and an output node, and is connected at its gate node to a third control signal ?CT via a third capacitance element. A fourth transistor is connected between the output node and a gate node of the third transistor, and is connected at its gate to the second node. An internal voltage at an intended level can be generated with low power consumption while efficiently using charges without causing an ineffective current flow.

Abstract: The decode circuit includes decode paths corresponding to gray-scale voltages. Each decode path has decode transistors connected serially and corresponding to display signal bits. In a selected decode path, the decode transistors connected serially are all turned on to transmit the corresponding gray-scale voltage to output node of the decode circuit. The gate of each of the decode transistors is connected to one signal line of first and second signal lines transmitting the corresponding display signal bits and inverted signals of the corresponding display signal bits, respectively. The other signal line not connected to the gate is disposed so as to create a parasitic capacitance similar to a gate capacitance between a node connected to the source or drain of the decode transistor and the other signal line. Accordingly, noise resistance in the decode circuit for gray-scale expression can be enhanced with suppressing increase in circuit area.

Abstract: A high-speed shift register circuit is provided. The shift register circuit includes a first transistor supplying a clock signal to a first output terminal, a second transistor discharging the first output terminal, a third transistor supplying the above clock signal to a second output terminal, and a fourth transistor discharging the second output terminal. The gates of the first and third transistors are both connected to a first node, and the gates of the second and fourth transistors are both connected to a second node. The first node is charged by a fifth transistor which is connected between the first node and a first input terminal and which has a gate connected to a second input end.

Abstract: A gradation potential generating circuit in a color liquid crystal display device includes 65 resistance elements connected in series and dividing a voltage applied between first and second nodes to generate 64 gradation potentials; a first current amplifier circuit provided corresponding to each gradation potential higher than a precharge potential of a data line and having charging capability higher than discharging capability; and a second current amplifier circuit provided corresponding to each gradation potential lower than the precharge potential and having discharging capability higher than charging capability.

Abstract: A first amplifier circuit (132) included in a voltage generating circuit (114) includes a differential circuit formed of P-type TFT elements (P101, P102) and N-type TFT elements (N101, N102), a constant current circuit (150a, 150b) and an N-type TFT element (N103). Constant current circuit (150a; 150b) includes a P-type TFT element (P132a; P132b), a capacitor (C132a; C132b), switches (S104a-S106a; S104b-S106b) and a resistance element (R132a; R132b). Capacitor (C132a; C132b) holds a voltage on a node (204; 208) in a voltage setting operation, and thus when a current is being supplied to the diode-connected P-type TFT element (P132a; P132b).

Abstract: A shift register has an output stage formed by a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a ground. Third and fourth transistors are connected in series between the gate of the first transistor (first node) and the ground. A second node between the third and fourth transistors is connected to a power source via a fifth transistor. The fifth transistor has its gate connected to the first node. Accordingly, when the third and fourth transistors are turned off to raise the first node in level, the fifth transistor is turned on, whereby a predetermined voltage is applied to the second node.

Abstract: Malfunction caused by leakage current of the transistor and shift in threshold voltage is prevented in the shift register in which the signal can be shifted bi-directionally. The bi-directional unit shift register includes a first transistor Q1 for providing a first clock signal CLK to an output terminal OUT, a second transistor Q2 for discharging the output terminal OUT based on a second clock signal, third and fourth transistors Q3, Q4 for providing first and second voltage signals Vn, Vr complementary to each other to a first node, which is a gate node of the first transistor Q1, and a fifth transistor Q5 connected between the first node and the output terminal OUT. The fifth transistor Q5 is in an electrically conducted state based on the first clock signal CLK when the gate of the transistor Q1 is at L (Low) level.

Abstract: A shift register has an output stage formed by a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a ground. Third and fourth transistors are connected in series between the gate of the first transistor (first node) and the ground. A second node between the third and fourth transistors is connected to a power source via a fifth transistor. The fifth transistor has its gate connected to the first node. Accordingly, when the third and fourth transistors are turned off to raise the first node in level, the fifth transistor is turned on, whereby a predetermined voltage is applied to the second node.

Abstract: Malfunction caused by leakage current of the transistor is prevented in the shift register in which the signal can be shifted bi-directionally. The bi-directional unit shift register includes a transistor Q1 between a clock terminal CK and an output terminal OUT, a transistor Q2 for discharging the output terminal OUT, and transistors Q3, Q4 for providing first and second voltage signals Vn, Vr, which are complementary to each other, to the first node or a gate node of the transistor Q1. Furthermore, a transistor Q5, having a gate connected to a second node or a gate node of the transistor Q2, for discharging the first node is arranged.

Abstract: In a shift register circuit, a defective operation while an output signal is not outputted and a drive capability lowering while the output signal is outputted are prevented. A unit shift register comprises a first transistor for supplying a clock signal inputted to a first clock terminal to an output terminal, and the first transistor is driven by a drive circuit. A second transistor is connected between the gate of the first transistor and the output terminal and has a gate connected to the first clock terminal. The second transistor connects the gate of the first transistor to the output terminal based on the clock signal when the gate of the first transistor is at L (Low) level.

Abstract: A pixel drive circuit includes a drain voltage increase limiter circuit composed of a TFT device provided between a node and the drain of a TFT device serving as a current source, a capacitor and a switch. In a data write mode, switches are turned on to allow drive current to flow from a data line to the TFT devices. Then, respective gate voltages of the TFT devices are held in respective capacitors. In a display mode, only a switch is turned on to form a current path from a supply voltage to the TFT devices through a light-emitting diode. The voltage on a node is held constant regardless of channel modulation. Accordingly, desired electric current flows through the light-emitting diode.

Abstract: A pulse number control circuit inputs, to a charge pump circuit, pulses of a number according to digital data constituted of weighted data bits. The charge pump circuit includes a pump capacitor connected between a first node to which the pulses are input and a second node, a switch element connected between the second node and an output node, and a bias circuit. According to a change of a voltage on the output node, the bias circuit changes a voltage on the second node with the same polarity.

Abstract: A unit shift register includes first and second transistors for supplying low supply voltage to an output terminal. First and second control signals which are complementary to each other are input to first and second control terminals, respectively. A third transistor is connected between the first transistor and first control terminal, and a fourth transistor is connected between the second transistor and second control terminal. The third and fourth transistors each have its drain connected to the gate of each other in a crossed manner.

Abstract: A shift register circuit comprises a first transistor between a gate line output terminal and a clock terminal, a second transistor between the gate line output terminal and a first power supply terminal, a third transistor between a carry signal output terminal and the clock terminal and a fourth transistor between the carry signal output terminal and the first power supply terminal. Gates of the second and fourth transistors are connected to each other. A fifth transistor connected between a gate of the first transistor and a second power supply terminal and a sixth transistor connected between a gate of the third transistor and the second power supply terminal have gates both of which are connected to an input terminal. With this constitution, it is possible to suppress an influence between two synchronous output signals outputted from the shift register circuit.