Abstract: A level shifter includes first and second P-type TFTs for latching a level of first and second output nodes, first and second N-type TFTs for setting the level of the first and second output nodes, and a drive circuit. The drive circuit includes third to eighth N-type TFTs providing, in response to rising and falling edges of an input signal, a voltage higher than a threshold voltage of the first and second N-type TFTs, between the gate and source of the first and second N-type TFTs, and includes first and second capacitors and a resistor element. Accordingly, even if an amplitude voltage of an input signal is smaller than the threshold voltage of the first and second N-type TFTs, the level shifter operates normally.

Abstract: A pixel drive circuit includes a drain voltage increase limiter circuit composed of a TFT device provided between a node and the drain of a TFT device serving as a current source, a capacitor and a switch. In a data write mode, switches are turned on to allow drive curent to flow from a data line to the TFT devices. Then, respective gate voltages of the TFT devices are held in respective capacitors. In a display mode, only a switch is turned on to form a current path from a supply voltage to the TFT devices through a light-emitting diode. The voltage on a node is held constant regardless of channel modulation. Accordingly, desired electric current flows through the light-emitting diode.

Abstract: The present drive circuit includes: a first N-type transistor connected between a power supply potential line and an output node; a P-type transistor connected between the power supply potential line and the gate of the first N-type transistor; a second N-type transistor forming a diode connected between the gate of the first N-type transistor and a prescribed node; and a differential amplifier for regulating the gate potential of the P-type transistor to match the potential at the prescribed node with the input potential.

Abstract: In an analog amplifier unit circuit included in a color liquid crystal display, an aluminum interconnection is formed to cover a gate electrode of an input transistor of a drive circuit, and capacitance between the gate electrode and the aluminum interconnection is used as an offset-compensating capacitor. Thus, the parasitic capacitance of the gate electrode of the input transistor can be made small, and the offset voltage can be canceled accurately, without increasing the area occupied by a capacitor.

Abstract: A MOS capacitor receiving a clock signal complementary to a sampling clock signal is provided at an input of a clocked inverter that is activated after sampling an input signal to perform level conversion. A charge pump operation of the MOS capacitor is performed in parallel with the activation of the clocked inverter. The power consumption of and the area occupied by a level conversion circuit converting a voltage amplitude of the input signal are reduced without deteriorating a high-speed operating characteristics.

Abstract: An offset-compensation drive circuit turns on first, second and third switches to charge a first capacitor to an offset voltage of a drive circuit, and thereafter turns off the first and second switches and turns on a fourth switch to charge a second capacitor to a first voltage loss caused by a parasitic capacitor of an input node of the drive circuit. Following this, the third and fourth switches are turned off and fifth and sixth switches are turned on. At this time as well, there occurs a second voltage loss due to the parasitic capacitor and thus an output voltage is equal to a difference between an input voltage and the second voltage loss. Supposing that the parasitic capacitor, the first capacitor and the second capacitor have the same capacitance value, the second voltage loss is one-sixth as large as the first voltage loss.

Abstract: A first amplifier circuit (132) included in a voltage generating circuit (114) includes a differential circuit formed of P-type TFT elements (P101, P102) and N-type TFT elements (N101, N102), a constant current circuit (150a, 150b) and an N-type TFT element (N103). Constant current circuit (150a; 150b) includes a P-type TFT element (P132a; P132b), a capacitor (C132a; C132b), switches (S104a-S106a; S104b-S106b) and a resistance element (R132a; R132b). Capacitor (C132a; C132b) holds a voltage on a node (204; 208) in a voltage setting operation, and thus when a current is being supplied to the diode-connected P-type TFT element (P132a; P132b).

Abstract: This pixel display circuit includes an EL drive circuit including serially connected EL element, a P-type transistor and a resistor element, a differential amplifier circuit setting a potential of the gate of P-type transistor such that a potential of a control node becomes equal to a potential of an input node, and an offset compensation circuit canceling an offset voltage of differential amplifier circuit. Accordingly, the factor of variations of the value of a current flowing through EL element becomes only a resistance value of resistor element, and therefore variations of display characteristics among pixels are reduced.

Abstract: A drive circuit includes a first level shift circuit outputting a potential higher than an input potential by a prescribed voltage; a pull-up circuit outputting to an output node a potential lower than an output potential of the first level shift circuit by the prescribed voltage; a second level shift circuit outputting a potential lower than the input potential by the prescribed voltage; a pull-down circuit outputting to the output node a potential higher than an output potential of the second level shift circuit by the prescribed voltage; and a capacitor connected between output nodes of the first and second level shift circuits. Accordingly, through-current is reduced.

Abstract: A differential amplification circuit generates a voltage difference corresponding to a voltage difference between an input node and an output node, across first and second nodes. An output circuit generates a voltage and a current corresponding to a voltage at a control node, on the output node. A switch element is provided between the first node and the control node. The differential amplification circuit and the output circuit, when a feedback loop is formed by turning-on of the switch element, operate so as to cause a voltage at the output node to coincide with a voltage at the input node. The switch element is turned off after the voltage at the output node becomes equal to the voltage at the input node by formation of the feedback loop. With such a construction, provided is a current amplifying circuit which is high in stability against oscillating and low in power consumption.

Abstract: A differential amplifier is used to determine the level of an output voltage of a charge pump circuit, and is operated in the voltage follower mode with a reference voltage being an input thereto for charging a capacitance element with a resultant output voltage of the amplifier circuit. Subsequently, a voltage to be compared that corresponds to the output voltage of the charge pump circuit is compared with the voltage stored in the capacitance element to generate an output signal by the differential amplifier. According to this output signal of the differential amplifier, the charge pump operation of the charge pump circuit is selectively activated. A power supply circuit is provided which stably generates an internal voltage at a desired voltage level.

Abstract: A sample hold circuit includes a first switch connected between a data line and a first node, a second switch connected between first node and a second node, a capacitor connected between the second node and a line of a common potential, and a drive circuit applying a potential equal to that of the second node to the first node and one of the electrodes of the liquid crystal cell. The first and second switches are turned on when a scanning line is at an “H” level.

Abstract: A gradation potential generating circuit in a color liquid crystal display device includes 65 resistance elements (R1 to R65) connected in series and dividing a voltage (VH?VL) applied between first and second nodes (N30, N31) to generate 64 gradation potentials (V1d to V64d); a first current amplifier circuit provided corresponding to each gradation potential (V33d to V64d) higher than a precharge potential (VPC) of a data line and having charging capability higher than discharging capability; and a second current amplifier circuit provided corresponding to each gradation potential (V1d to V32d) lower than the precharge potential (VPC) and having discharging capability higher than charging capability.

Abstract: The decode circuit includes decode paths corresponding to gray-scale voltages. Each decode path has decode transistors connected serially and corresponding to display signal bits. In a selected decode path, the decode transistors connected serially are all turned on to transmit the corresponding gray-scale voltage to output node of the decode circuit. The gate of each of the decode transistors is connected to one signal line of first and second signal lines transmitting the corresponding display signal bits and inverted signals of the corresponding display signal bits, respectively. The other signal line not connected to the gate is disposed so as to create a parasitic capacitance similar to a gate capacitance between a node connected to the source or drain of the decode transistor and the other signal line. Accordingly, noise resistance in the decode circuit for gray-scale expression can be enhanced with suppressing increase in circuit area.

Abstract: A level shifter includes first and second P type thin film transistors (TFTs) and first and second N type TFTs for latching levels of first and second output nodes, third and fourth N type TFTs for setting levels of the first and second output nodes, and first and second resistance elements and first and second capacitors for applying, between the gate-source of the third and fourth N type TFTs, a voltage higher than a voltage of an input signal, in response to rising and falling edges of the input signal respectively.

Abstract: A gradation potential generating circuit of a color liquid crystal display apparatus includes a first ladder resistor circuit having a relatively high resistance value and generating first to sixty-fourth gradation potentials by dividing a power supply voltage to apply them to first to sixty-fourth nodes, and a second ladder resistor circuit having a relatively low resistance value, activated during an initial predetermined period of a time period while a selected gradation potential is applied to a data line, and generating first to sixty-fourth gradation potentials by dividing the power supply voltage to apply them to first to sixty-fourth nodes, and 65 switches. Therefore, since the ladder resistor circuit having low resistance is activated in a pulsed manner, the data line can be charged/discharged at a high-speed with low current consumption.

Abstract: In the color liquid crystal display, an insulating substrate having an analog amplifier which is likely to suffer failure formed thereon, and an insulating substrate having a circuit portion other than the analog amplifier formed thereon are separately prepared and quality-tested, and only the insulating substrate of good quality is mounted on the insulating substrate of good quality. This can increase yield of the color liquid crystal display compared to the conventional case where the entire color liquid crystal display is formed on a single insulating substrate.

Abstract: An internal voltage generation circuit and a voltage detection circuit for stably generating an internal voltage at a desired voltage level are provided. The voltage detection circuit includes an insulated gate field effect transistor receiving a reference voltage at a gate thereof and a voltage dropping element group connected in series between the insulated gate field effect transistor and an internal node. The reference voltage is generated by resistance-dividing a power supply voltage including a voltage drop and a threshold voltage of the insulated gate field effect transistor as its voltage components. When a voltage difference between the reference voltage and the internal voltage attains at least a prescribed value, a current flows through the voltage dropping element group and the insulated gate field effect transistor, and a voltage of a detection node decreases, and a lowering in the internal voltage is detected.

Abstract: The present drive circuit includes: a first N-type transistor connected between a power supply potential line and an output node; a P-type transistor connected between the power supply potential line and the gate of the first N-type transistor; a second N-type transistor forming a diode connected between the gate of the first N-type transistor and a prescribed node; and a differential amplifier for regulating the gate potential of the P-type transistor to match the potential at the prescribed node with the input potential.

Abstract: A gate of an N-channel MOS transistor driving an output node is driven through a capacitance element in accordance with an input signal. A voltage on a source node of the drive transistor is applied as an output signal to an output node. Consequently, it is possible to perform level conversion of a voltage at a low level of the input signal having a higher voltage than the source node voltage of the drive transistor. It is thus possible to achieve a level converting circuit that can reduce the number of manufacturing steps, and can perform the level conversion of any logical level of the input signal.