Abstract: A memory device may include a memory core block, a data patch unit, a Cyclic Redundancy Check (CRC) generating unit, and/or a serializer. The data patch unit may be configured to patch parallel data read from the memory core block in response to a first read pulse. The CRC generating unit may be configured to generate the CRC code based on the parallel data in response to a second read pulse, the second read pulse delayed by a period of time from if the first read pulse is generated. The serializer may be configured to convert the parallel data to serial data in response to the first read pulse, and/or arrange the CRC code in a order for a number of bits of the serial data to generate a systematic code.

Abstract: A multi-port memory device providing various frequencies for ports is disclosed. The multi-port memory device includes a memory core, a clock generator and a plurality of ports. The clock generator generates an internal clock signal based on an external clock signal. Each of the ports has a local clock generator that generates a local clock signal having a predetermined frequency based on the internal clock signal and accesses the memory core in response to the local clock signal. The multi-port memory device may generate various frequencies for ports without increasing the number of pins for receiving clock signals.

Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.

Abstract: A multi-port semiconductor device and method thereof are provided. In an example, the multi-port memory device may include a clock generating unit receiving an external clock signal having a given frequency and a given phase, the clock generating unit generating a plurality of local clock signals by adjusting at least one of the given frequency and given phrase of the received external clock signal such that at least one of the plurality of local clock signals have at least one of a different frequency and a different phase as compared to the given frequency and given phrase, respectively, of the received external clock signal.

Abstract: An input/output data pipeline circuit of a semiconductor memory device includes a first transmitting unit, a control signal generating unit, and a second transmitting unit. The first transmitting unit receives data stored in a memory cell and transmits data to an input/output driver in response to activation of a first switching signal and a second switching signal. The control signal generating unit receives a clock signal from the semiconductor memory device and, corresponding to the frequency of the clock signal, outputs a control signal, the first switching signal, and the second switching signal. The second transmitting unit transmits data to the input/output driver in response to activation of the control signal. The first transmitting unit and the second transmitting unit are alternatively activated.

Abstract: A multi-port memory device providing various frequencies for ports is disclosed. The multi-port memory device includes a memory core, a clock generator and a plurality of ports. The clock generator generates an internal clock signal based on an external clock signal. Each of the ports has a local clock generator that generates a local clock signal having a predetermined frequency based on the internal clock signal and accesses the memory core in response to the local clock signal. The multi-port memory device may generate various frequencies for ports without increasing the number of pins for receiving clock signals.

Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.

Abstract: There is provided a Delay Locked Loop (DLL) including a duty cycle correction circuit capable of controlling a duty error, when the duty error is generated in the DLL. The duty cycle correction circuit controls amounts of electric charges accumulated in storage units, in response to switching control signals received from the external, and outputs duty rate control signals each corresponding to a difference between the amounts of electric charges accumulated in the storage units. Therefore, the DLL including the duty cycle correction circuit can correct a duty cycle of a reference clock signal, in response to the duty rate control signals, and can output a reference clock signal with a duty cycle of 50%.

Abstract: A synchronous memory device, which includes a read command buffer, a replica circuit, and a latency circuit. The read command buffer provides a read signal in response to a read command. The replica circuit provides a transfer signal whose time difference with respect to the feedback clock signal is substantially identical to a period that it takes a read command buffer to provide the read signal. The latency circuit receives the read signal, and provides a latency signal having a difference of a predetermined time corresponding to CAS latency with respect to the read signal in response to the transfer signal.

Abstract: There is provided a Delay Locked Loop (DLL) including a duty cycle correction circuit capable of controlling a duty error, when the duty error is generated in the DLL. The duty cycle correction circuit controls amounts of electric charges accumulated in storage units, in response to switching control signals received from the external, and outputs duty rate control signals each corresponding to a difference between the amounts of electric charges accumulated in the storage units. Therefore, the DLL including the duty cycle correction circuit can correct a duty cycle of a reference clock signal, in response to the duty rate control signals, and can output a reference clock signal with a duty cycle of 50%.

Abstract: A semiconductor memory device optimizes current consumption by using proper sub-bank arrangement and at least two different kinds of LIO sense amplifiers having different driving capabilities. The driving capabilities of the LIO sense amplifiers are controlled in a tapered manner depending on whether a corresponding sub-bank of the LIO sense amplifier is arranged nearer to, or farther away from, its corresponding GIO sense amplifier. In other words, the farther that a sub-bank of an LIO sense amplifier is away from its corresponding GIO sense amplifier, the greater its driving capability.

Abstract: Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.

Abstract: There is provided a Delay Locked Loop (DLL) including a duty cycle correction circuit capable of controlling a duty error, when the duty error is generated in the DLL. The duty cycle correction circuit controls amounts of electric charges accumulated in storage units, in response to switching control signals received from the external, and outputs duty rate control signals each corresponding to a difference between the amounts of electric charges accumulated in the storage units. Therefore, the DLL including the duty cycle correction circuit can correct a duty cycle of a reference clock signal, in response to the duty rate control signals, and can output a reference clock signal with a duty cycle of 50%.

Abstract: A semiconductor memory device optimizes current consumption by using proper sub-bank arrangement and at least two different kinds of LIO sense amplifiers having different driving capabilities. The driving capabilities of the LIO sense amplifiers are controlled in a tapered manner depending on whether a corresponding sub-bank of the LIO sense amplifier is arranged nearer to, or farther away from, its corresponding GIO sense amplifier. In other words, the farther that a sub-bank of an LIO sense amplifier is away from its corresponding GIO sense amplifier, the greater its driving capability.

Abstract: There is provided a Delay Locked Loop (DLL) including a duty cycle correction circuit capable of controlling a duty error, when the duty error is generated in the DLL. The duty cycle correction circuit controls amounts of electric charges accumulated in storage units, in response to switching control signals received from the external, and outputs duty rate control signals each corresponding to a difference between the amounts of electric charges accumulated in the storage units. Therefore, the DLL including the duty cycle correction circuit can correct a duty cycle of a reference clock signal, in response to the duty rate control signals, and can output a reference clock signal with a duty cycle of 50%.

Abstract: An input/output data pipeline circuit of a semiconductor memory device includes a first transmitting unit, a control signal generating unit, and a second transmitting unit. The first transmitting unit receives data stored in a memory cell and transmits data to an input/output driver in response to activation of a first switching signal and a second switching signal. The control signal generating unit receives a clock signal from the semiconductor memory device and, corresponding to the frequency of the clock signal, outputs a control signal, the first switching signal, and the second switching signal. The second transmitting unit transmits data to the input/output driver in response to activation of the control signal. The first transmitting unit and the second transmitting unit are alternatively activated.

Abstract: An input receiver controls an offset voltage by using an output feedback signal to improve a sense speed. The input receiver includes a pre-amplifier that controls an offset voltage in response to a feedback signal and amplifies an input signal with reference to a reference voltage. A sense amplifier amplifies an output signal and an inverted output signal of the pre-amplifier in response to a clock signal. A latch circuit latches an output signal and an inverted output signal of the sense amplifier. An inversion circuit uses the reference voltage as a power supply voltage and inverts an inverted output signal of the latch circuit. In addition, an output signal of the inversion circuit is supplied as the feedback signal. Alternatively, the output signal of the latch circuit may be directly supplied to the pre-amplifier as the feedback signal while not using the inversion circuit.

Abstract: An input receiver controls an offset voltage by using an output feedback signal to improve a sense speed. The input receiver includes a pre-amplifier that controls an offset voltage in response to a feedback signal and amplifies an input signal with reference to a reference voltage. A sense amplifier amplifies an output signal and an inverted output signal of the pre-amplifier in response to a clock signal. A latch circuit latches an output signal and an inverted output signal of the sense amplifier. An inversion circuit uses the reference voltage as a power supply voltage and inverts an inverted output signal of the latch circuit. In addition, an output signal of the inversion circuit is supplied as the feedback signal. Alternatively, the output signal of the latch circuit may be directly supplied to the pre-amplifier as the feedback signal while not using the inversion circuit.