Abstract: A storage device includes a memory device including one or more memory blocks including first sub-areas and second sub-areas configured to store higher level data than the first sub-areas, and a controller configured to use the first sub-areas before the second sub-areas in order to store data in the memory device.

Abstract: The present application relates to a plant-soaked solution including a saccharide containing allulose and a method of preparing the same.

Abstract: The present application relates to a plant-soaked solution comprising sugars containing tagatose and to a method for producing same.

Abstract: A memory system may include a storage device and a memory controller. The storage device may include a plurality of memory blocks. Each of the memory blocks may include a plurality of pages. The memory controller may perform a maintenance management operation including predetermined numbers of sub-operations performed for a first period in each first cycle on the storage device, wherein the memory controller is configured to increase a reservation number of the sub-operations when a first type command requested from an external device is processed at a time of triggering the sub-operations, and determine a trigger interval of the sub-operations based on the reservation number.

Abstract: A controller includes a clock frequency determiner configured to determine a type of a read operation corresponding to a read request based on the read request received from a host, and to determine a clock frequency according to the type, a clock generator configured to generate a clock according to the determined clock frequency, and a command generator configured to generate a read command corresponding to the read request using the clock.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system may divide and manage the plurality of memory dies into a plurality of memory die groups, may set a first super memory block including at least one of memory blocks included in a first memory die group, and a second super memory block including at least one of memory blocks included in a second memory die group, may determine whether to set an extended super memory block in which all or part of the first super memory block and all or part of the second super memory block are merged, and may write a write data to the extended super memory block in an interleaving manner when writing the write data requested by a host.

Abstract: A memory controller includes a plurality of processors, a memory device and a memory manager. The memory device includes a plurality of segments, which are divided into a plurality of segment groups, to which group identifiers are respectively assigned. The memory manager is configured to map a first buffer identifier to a first group identifier from among the group identifiers, select one or more segments only from a first segment group, to which the first group identifier is assigned among the plurality of segment groups, map the first buffer identifier to the one or more segments, and allocate, to a first processor from among the plurality of processors, the first buffer identifier and the one or more segments.

Abstract: A memory system comprising: a memory device configured to store, in a non-volatile storage area included therein, a list of a plurality of performance classes and a table of performance information representing a group of performance parameter values for each of the plurality of performance classes, and a controller configured to provide the list to an external device according to a first request received from the external device, select one of the plurality of performance classes within the table according to a second request received from the external device, and control an operation of the memory device at an operation speed and in an operation method according to the performance parameter values corresponding to the selected performance class.

Abstract: A storage device includes a memory device including one or more memory blocks including first sub-areas and second sub-areas configured to store higher level data than the first sub-areas, and a controller configured to use the first sub-areas before the second sub-areas in order to store data in the memory device.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system may divide and manage the plurality of memory dies into a plurality of memory die groups, may set a first super memory block including at least one of memory blocks included in a first memory die group, and a second super memory block including at least one of memory blocks included in a second memory die group, may determine whether to set an extended super memory block in which all or part of the first super memory block and all or part of the second super memory block are merged, and may write a write data to the extended super memory block in an interleaving manner when writing the write data requested by a host.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system may divide and manage the plurality of memory dies into a plurality of memory die groups, may set a first super memory block including at least one of memory blocks included in a first memory die group, and a second super memory block including at least one of memory blocks included in a second memory die group, may determine whether to set an extended super memory block in which all or part of the first super memory block and all or part of the second super memory block are merged, and may write a write data to the extended super memory block in an interleaving manner when writing the write data requested by a host.

Abstract: An electronic device includes a memory controller selecting map data to be output to a host. The memory controller includes an address counter and a map data selector. The address counter counts a number of times a logical block address corresponding to a request is received based on the request received from the host and outputs an activation signal indicating that an index to which the logical block address belongs is an activation index when an activation count corresponding to the index is equal to or greater than a preset value, the activation count being generated based on a counting result. The map data selector selects map data to be output to the host based on the activation signal. The address counter decreases the activation count by a preset size when a size of the selected map data exceeds a storage capacity of the host allocated for storing map data.

Abstract: A controller controlling a memory device includes an elapsed time calculator receiving a plurality of absolute times from a host when a state of a memory system including the memory device is changed between an active state and an inactive state, the plurality of absolute times including first, second, and third absolute times, calculating an average hibernation time interval between the first and second absolute times, and calculating a system time based on the third absolute time and the average hibernation time interval. The controller further includes a flash translation layer calculating expected usage of the memory device during a monitoring time interval based on the system time, calculating excess usage based on actual usage of the memory device during the monitoring time interval and the expected usage, and controlling the memory device to program data in a single level cell mode until the excess usage is fully consumed.

Abstract: A controller controlling a memory device includes an elapsed time calculator suitable for receiving an absolute time from a host whenever a state is changed between an active state and an inactive state, calculating an average hibernation elapsed time for elapsed times between first and second absolute times, and calculating a system time based on a third absolute time and the average hibernation elapsed time, and a flash translation layer suitable for controlling a program operation for the memory device in response to a program command for a memory region, calculating a program operation time for the memory region based on the system time, and controlling a read operation for the memory device using a read voltage, which is determined based on an elapsed time since the program operation time, in response to a read command for the memory region.

Abstract: An electronic device includes a memory controller selecting map data to be output to a host. The memory controller includes an address counter and a map data selector. The address counter counts a number of times a logical block address corresponding to a request is received based on the request received from the host and outputs an activation signal indicating that an index to which the logical block address belongs is an activation index when an activation count corresponding to the index is equal to or greater than a preset value, the activation count being generated based on a counting result. The map data selector selects map data to be output to the host based on the activation signal. The address counter decreases the activation count by a preset size when a size of the selected map data exceeds a storage capacity of the host allocated for storing map data.

Abstract: A controller controlling a memory device includes an elapsed time calculator suitable for receiving an absolute time from a host whenever a state is changed between an active state and an inactive state, calculating an average hibernation elapsed time for elapsed times between first and second absolute times, and calculating a system time based on a third absolute time and the average hibernation elapsed time, and a flash translation layer suitable for controlling a program operation for the memory device in response to a program command for a memory region, calculating a program operation time for the memory region based on the system time, and controlling a read operation for the memory device using a read voltage, which is determined based on an elapsed time since the program operation time, in response to a read command for the memory region.

Abstract: A controller controlling a memory device includes an elapsed time calculator receiving a plurality of absolute times from a host when a state of a memory system including the memory device is changed between an active state and an inactive state, the plurality of absolute times including first, second, and third absolute times, calculating an average hibernation time interval between the first and second absolute times, and calculating a system time based on the third absolute time and the average hibernation time interval. The controller further includes a flash translation layer calculating expected usage of the memory device during a monitoring time interval based on the system time, calculating excess usage based on actual usage of the memory device during the monitoring time interval and the expected usage, and controlling the memory device to program data in a single level cell mode until the excess usage is fully consumed.

Abstract: A method of operating a data storage device includes receiving size information of a region needed for a data transaction from a host, calculating the sum of a size of a first region available in an invisible region-to-user and a size of a second region available in a visible region-to-user based on the size information, and communicating a response indicating possibility of the data transaction to the host based on a calculation result.

Abstract: A method of operating a data storage device includes receiving size information of a region needed for a data transaction from a host, calculating the sum of a size of a first region available in an invisible region-to-user and a size of a second region available in a visible region-to-user based on the size information, and communicating a response indicating possibility of the data transaction to the host based on a calculation result.

Abstract: A DED arc 3D alloy metal powder cored printing method, according to an embodiment of the present invention, comprises the steps of: (a) connecting a 3D printing part to a first electrode via a ground line, contacting a second electrode, in which an electrode contact tip is tapped on a peripheral surface of an alloy metal powder cored wire, and then generating an arc by a potential difference between the first electrode and the second electrode to melt the tip of the alloy metal powder cored wire and the surface of the printing part at the same time; (b) forming a monolayer by mixing and solidifying the melt of the alloy metal powder cored wire and the melt of the surface of the printing part; and (c) stacking the monolayer by continuously performing a monolayer overlay, layer-upon-layer.