Abstract: The present invention relates to a fusion protein comprising a SARS-CoV-2-derived receptor-binding domain and a nucleocapsid protein, and the use thereof. The fusion protein comprising a coronavirus-derived receptor-binding domain and a nucleocapsid protein is highly applicable to a multivalent vaccine composition having greatly improved in-vivo half-life and remarkably superior efficacy compared to an immunogenic composition comprising only a receptor-binding domain. In particular, the fusion protein can greatly improve the titer of the coronavirus-specific antibody formation and T-cell immune response, and is thus useful for the prevention and treatment of coronaviruses comprising SARS-CoV-2.

Abstract: A calculation code generation circuit performs calibration using a counter, and a digital correction circuit including the same. The calculation code generation circuit performs a calculation process according to first and second modes, the calculation process including generating a first code by sampling a first value of the count code, generating a second code by sampling a second value of the count code, generating first and second calculation codes using the first and second codes in the first and second modes, respectively, and generating, in a calibration disable state, a third calculation code using the first and second calculation codes generated in the first and second modes, respectively, to remove the influence of the comparison offset or comparison performance of a comparator, thereby removing a calibration error.

Abstract: A calculation code generation circuit performs calibration using a counter, and a digital correction circuit including the same. The calculation code generation circuit performs a calculation process according to first and second modes, the calculation process including generating a first code by sampling a first value of the count code, generating a second code by sampling a second value of the count code, generating first and second calculation codes using the first and second codes in the first and second modes, respectively, and generating, in a calibration disable state, a third calculation code using the first and second calculation codes generated in the first and second modes, respectively, to remove the influence of the comparison offset or comparison performance of a comparator, thereby removing a calibration error.

Abstract: Disclosed are a carbon nanomaterial pellet and a method for preparing same. More particularly, it relates to a carbon nanomaterial pellet having a specific size and a high apparent density prepared by a simple process using only a rotary tablet press without mixing a carbon nanomaterial powder with a solvent or an additive, which is capable of solving the powder dust problem occurring when preparing a polymer composite from a carbon nanomaterial in the form of powder, thus improving physical properties and remarkably reducing cost of packaging and transportation, and a method for preparing the carbon nanomaterial pellet from a carbon nanomaterial powder.

Abstract: Disclosed is a method for preparing a carbon nanomaterial/polymer composite. More particularly, it relates to an improved method for preparing a carbon nanomaterial/polymer composite capable of solving a dust problem of a carbon nanomaterial powder and a layer separation problem due to large density difference between the carbon nanomaterial powder and a polymer pellet and providing superior physical properties of the composite, whereby an additive used to prepare the carbon nanomaterial/polymer composite is mixed with the carbon nanomaterial powder and prepared into a pellet, which is then mixed with the polymer pellet.

Abstract: The present invention, which relates to an apparatus for collecting data at multi-points, suggests an apparatus connecting analog blocks obtaining the same channel data in series with each other and connecting analog blocks obtaining different channel data in parallel with each other to collect data. The suggested apparatus includes a channel data collecting group including at least two channel data collecting units having data obtaining modules collecting channel data at different points and connected in series with each other; and a channel data processing unit including the channel data collecting units connected in parallel with each other and controlling each of the data obtaining module so as to allow each of the channel obtaining module to shift the channel data by a predetermined size.

Abstract: Disclosed are a carbon nanomaterial pellet and a method for preparing same. More particularly, it relates to a carbon nanomaterial pellet having a specific size and a high apparent density prepared by a simple process using only a rotary tablet press without mixing a carbon nanomaterial powder with a solvent or an additive, which is capable of solving the powder dust problem occurring when preparing a polymer composite from a carbon nanomaterial in the form of powder, thus improving physical properties and remarkably reducing cost of packaging and transportation, and a method for preparing the carbon nanomaterial pellet from a carbon nanomaterial powder.

Abstract: Provided is a time-domain voltage comparator including a voltage-time converter. The voltage-time converter includes a conversion unit and an output unit. The conversion unit includes a first MOS transistor which shifts a voltage level of the first detection node according to an external first voltage signal, and a second MOS transistor which shifts a voltage level of the second detection node according to an external second voltage signal. The output unit generates first and second output signals in response to voltages of the first and second detection nodes. The output unit determines a shifted time of the first output signal according to a voltage level of the first detection node and determines a shifted time of the second output signal according to a voltage level of the second detection node.

Abstract: In the example embodiments, test signals sent from a transmitting system are received at a receiving system. The receiving system generates a determination signal indicating, in one embodiment, whether received signals have a desired relationship with respect to a clock signal at the receiving system. Timing of the clock signal or timing for transmitting signals may be adjusted based on the determination. In another embodiment, the receiving system generates a determination signal indicating whether the pulse width of a lone pulse signal equals a desired time interval. Equalization or pre-emphasis is controlled based on the determination signal.

Abstract: A memory controller includes an I/O circuit, a read latency detector and a clock domain synchronizer. The I/O circuit transmits a first signal to a semiconductor memory device, receives a reflected signal returned from the semiconductor memory device, and delays the reflected signal in response to a delay selection signal to generate a second signal. The reflected signal is provided by reflection of the first signal from the semiconductor memory device. The read latency detector generates the first signal in response to a system clock signal, and generates a read latency signal in response to the system clock signal, a hold signal, and the second signal. The clock domain synchronizer generates the delay selection signal and the hold signal in response to the system clock signal and the second signal.

Abstract: In the example embodiments, test signals sent from a transmitting system are received at a receiving system. The receiving system generates a determination signal indicating, in one embodiment, whether received signals have a desired relationship with respect to a clock signal at the receiving system. Timing of the clock signal or timing for transmitting signals may be adjusted based on the determination. In another embodiment, the receiving system generates a determination signal indicating whether the pulse width of a lone pulse signal equals a desired time interval. Equalization or pre-emphasis is controlled based on the determination signal.

Abstract: In the example embodiments, test signals sent from a transmitting system are received at a receiving system. The receiving system generates a determination signal indicating, in one embodiment, whether received signals have a desired relationship with respect to a clock signal at the receiving system. Timing of the clock signal or timing for transmitting signals may be adjusted based on the determination. In another embodiment, the receiving system generates a determination signal indicating whether the pulse width of a lone pulse signal equals a desired time interval. Equalization or pre-emphasis is controlled based on the determination signal.

Abstract: In a circuit, memory controller, memory system, and method for correcting skew among a plurality of communication channels used in communicating with a memory circuit, the circuit for correcting skew includes a transmitting circuit for transmitting a reference signal to input ends of the plurality of channels and through the plurality of channels, and a plurality of receiving circuits for receiving at the input ends of the plurality of channels a respective plurality of reflected signals, the reflected signals being reflected from respective output ends of the plurality of channels. A detection circuit receives the reflected signals and detects relative signal propagation time differences between the plurality of channels. A delay circuit coupled to at least one of the channels sets a signal propagation delay in the at least one of the channels based on the detected relative signal propagation time differences.

Abstract: Provided is a time-domain voltage comparator including a voltage-time converter. The voltage-time converter includes a conversion unit and an output unit. The conversion unit includes a first MOS transistor which shifts a voltage level of the first detection node according to an external first voltage signal, and a second MOS transistor which shifts a voltage level of the second detection node according to an external second voltage signal. The output unit generates first and second output signals in response to voltages of the first and second detection nodes. The output unit determines a shifted time of the first output signal according to a voltage level of the first detection node and determines a shifted time of the second output signal according to a voltage level of the second detection node.

Abstract: A data transceiver system may include an error corrector. The error corrector may include a plurality of delay units, each delay unit being configured to delay a corresponding data signal among a plurality of data signals by a time in response to a corresponding delay code among a plurality of delay codes and outputting the delayed data signal, an error detector configured to receive the plurality of delay codes, determine whether an error has occurred, and output an error signal according to the determination in a data frame lock operation, and a delay controller configured to set initial values of the plurality of delay codes to a predetermined value, vary and output each of the plurality of delay codes in response to a lock signal, and reset initial values the plurality of delay codes in response to the error signal in the data frame lock operation.

Abstract: A transceiver for controlling a swing width of an output voltage includes a transmitter and a receiver for receiving an output voltage of a transmitter. The transmitter includes a first signal converter that outputs changed data generated by changing a voltage level of data in response to a mode control signal for selecting a test mode or a normal mode, an output voltage control circuit for controlling a voltage level of an output node of the transmitter in response to the changed data, and a first termination circuit for supplying a changed power supply voltage generated by changing a voltage level of a power supply voltage of the output node of the transmitter, or is turned off, in response to a test mode enable signal or the changed data. The receiver includes a second termination circuit that operates as a resistor having a resistance value that varies in response to the test mode enable signal or a test mode disable signal.

Abstract: In one embodiment, the semiconductor device includes at least one circuit element configured to generate output data. At least one control circuit is configured to adaptively control a power of the output data based on feedback from a receiving semiconductor device, which receives the output data.

Abstract: In a circuit and method for correcting skew among a plurality of communication channels used in communicating with a memory circuit, and in a memory controller and memory controlling method, and in a memory system and method, the circuit for correcting skew includes a transmitting circuit for transmitting a reference signal to input ends of the plurality of channels and through the plurality of channels, and a plurality of receiving circuits for receiving at the input ends of the plurality of channels a respective plurality of reflected signals, the reflected signals being reflected from respective output ends of the plurality of channels. A detection circuit receives the reflected signals and detects relative signal propagation time differences between the plurality of channels. A delay circuit coupled to at least one of the channels sets a signal propagation delay in the at least one of the channels based on the detected relative signal propagation time differences.

Abstract: A stress detection circuit includes a function block and a detection signal generation circuit. The function block outputs a first voltage such that the first voltage is varied depending on an extent that the function block is stressed. The detection signal generation circuit generates a stress detection signal based on the first voltage and a second voltage during a test mode. The stress detection signal represents integration of the function block, and a level of the second voltage corresponds to a level of the first voltage before the function block is stressed.

Abstract: A communication system using multi-phase clock signals. The communication system includes a transmitter and a receiver. The transmitter outputs first data and a clock signal based on first multi-phase clock signals, and performs a coarse lock operation on the clock signal in response to a bit lock detection signal indicating whether or not the first data are bit-locked. The receiver receives the first data and the clock signal from the transmitter, generates second multi-phase clock signals based on the clock signal, generates second data by sampling the first data based on the second multi-phase clock signals, and performs a fine lock operation on the second multi-phase clock signals in response to the bit lock detection signal. Therefore, a jitter noise may be reduced and a size of a multi-phase clock generator included in the receiver may be reduced.