Patents by Inventor Young Do Hur
Young Do Hur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7830999Abstract: An apparatus for generating a clock signal of a semiconductor memory includes a first shifting unit that outputs first shifting signals using at least one periodic signal, a control signal generating unit that outputs multiplexing control signals using an inverted clock signal, a second shifting unit that outputs second shifting signals using at least one of the periodic signals, a correcting unit that outputs correction signals having an intermediate phase between the phase of the first shifting signals and the phase of the second shifting signals on the basis of a bias signal applied thereto, a combination unit that combines the first shifting signals and the correction signals to output combined signals, a multiplexing unit that selectively outputs the combined signals on the basis of multiplexing control signals, and a driving unit that drives the clock signal and the inverted clock signal based on the output of the multiplexing unit.Type: GrantFiled: December 29, 2006Date of Patent: November 9, 2010Inventor: Young-Do Hur
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Patent number: 7831405Abstract: A semiconductor package includes an input pin that receives a first signal from the outside of the semiconductor package, a pad that is coupled to the input pin, and a test mode driving circuit that receives the first signal from the pad and outputs a plurality of test mode signals to drive a test apparatus in a semiconductor chip.Type: GrantFiled: July 17, 2007Date of Patent: November 9, 2010Assignee: Hynix Semiconductor Inc.Inventor: Young Do Hur
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Patent number: 7768842Abstract: A voltage generating circuit for semiconductor memory devices for use in avoiding the occurrence of leakage currents associated with parasitic diodes is presented. The circuit controls and stabilizes the generation of a fedback negative voltage to prevent parasitic diode malfunctions by a in a wordline driver. The voltage generating circuit includes a controller being fedback the negative voltage and detecting a potential difference between backbias voltage provided to a substrate of the cell and the negative voltage to generate a control signal. The voltage generating circuit also includes a voltage generator being fedback the negative voltage to detect a level thereof, and which subsequently generates and provides the negative voltage in response to the detected results of the negative voltage and the control signal.Type: GrantFiled: September 10, 2008Date of Patent: August 3, 2010Assignee: Hynix Semiconductor Inc.Inventors: Young Do Hur, Yeon Uk Kim
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Patent number: 7751230Abstract: The negative voltage generating device includes a current interrupting controller, a voltage generating controller, and a negative voltage generator. The current interrupting controller outputs a current interrupting control signal in response to a control signal, which is enabled during the application of a power-up signal. The voltage generating controller compares a first reference voltage to a feedback voltage in response to the current interrupting control signal and outputs a voltage generating control signal. The negative voltage generator generates the feedback voltage and a second negative voltage by receiving the first negative voltage in response to the voltage generating control signal.Type: GrantFiled: September 10, 2008Date of Patent: July 6, 2010Assignee: Hynix Semiconductor Inc.Inventors: Yeon Uk Kim, Young Do Hur
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Publication number: 20100019810Abstract: A circuit for generating negative voltage of a semiconductor memory apparatus includes a first detecting unit configured to generate a first detecting signal by detecting a first negative voltage level, a first negative voltage generating unit configured to generate the first negative voltage in response to the first detecting signal, a second detecting unit configured to generate a second detecting signal by detecting the second negative voltage level, a timing controlling unit configured to output the second detecting signal as an enable signal when a power up signal is enabled and the first detecting signal is disabled, and a second negative voltage generating unit configured to generate the second negative voltage in response to the enable signal.Type: ApplicationFiled: December 23, 2008Publication date: January 28, 2010Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Yeon Uk Kim, Young Do Hur
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Publication number: 20090262586Abstract: A voltage generating circuit for semiconductor memory devices for use in avoiding the occurrence of leakage currents associated with parasitic diodes is presented. The circuit controls and stabilizes the generation of a fedback negative voltage to prevent parasitic diode malfunctions by a in a wordline driver. The voltage generating circuit includes a controller being fedback the negative voltage and detecting a potential difference between backbias voltage provided to a substrate of the cell and the negative voltage to generate a control signal. The voltage generating circuit also includes a voltage generator being fedback the negative voltage to detect a level thereof, and which subsequently generates and provides the negative voltage in response to the detected results of the negative voltage and the control signal.Type: ApplicationFiled: September 10, 2008Publication date: October 22, 2009Inventors: Young Do HUR, Yeon Uk KIM
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Publication number: 20090261792Abstract: The negative voltage generating device includes a current interrupting controller, a voltage generating controller, and a negative voltage generator. The current interrupting controller outputs a current interrupting control signal in response to a control signal, which is enabled during the application of a power-up signal. The voltage generating controller compares a first reference voltage to a feedback voltage in response to the current interrupting control signal and outputs a voltage generating control signal. The negative voltage generator generates the feedback voltage and a second negative voltage by receiving the first negative voltage in response to the voltage generating control signal.Type: ApplicationFiled: September 10, 2008Publication date: October 22, 2009Inventors: Yeon Uk KIM, Young Do HUR
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Publication number: 20090240460Abstract: A test circuit includes a first reset pulse generator configured to generate a first reset pulse when a test mode is performed or when power is up, a test mode maintenance signal generator configured to provide a test mode maintenance signal activated in response to a predetermined consecutive test information data, the activation of the test mode maintenance signal being controlled by the first reset pulse, a second reset pulse generator configured to generate a second reset pulse when the test information data is received as a predetermined test mode reset data or when power is up, and a test mode selection signal generator configured to receive the test information data provided from the test mode maintenance signal generator and the test mode maintenance signal and to generate a specific test mode selection signal, the activation of the specific test mode selection signal being controlled by the second reset pulse.Type: ApplicationFiled: June 2, 2009Publication date: September 24, 2009Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Young Do Hur
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Publication number: 20080315937Abstract: An apparatus for generating an internal voltage in a semiconductor integrated circuit includes a first voltage generating unit configured to detect a feedback voltage level of a first internal voltage and perform a pumping operation, thereby generating a first internal voltage, and a second voltage generating unit configured to generate a second internal voltage by detecting a feedback voltage level of the second internal voltage, performing level shifting on the detected feedback voltage level, receiving the first internal voltage, and generating the second internal voltage based on the level shifted feedback voltage signal and the received first internal voltage.Type: ApplicationFiled: December 21, 2007Publication date: December 25, 2008Applicant: HYNIX SEMINCONDUCTOR, INC.Inventor: Young-Do Hur
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Publication number: 20080278189Abstract: A test circuit includes a first reset pulse generator configured to generate a first reset pulse when a test mode is performed or when power is up, a test mode maintenance signal generator configured to provide a test mode maintenance signal activated in response to a predetermined consecutive test information data, the activation of the test mode maintenance signal being controlled by the first reset pulse, a second reset pulse generator configured to generate a second reset pulse when the test information data is received as a predetermined test mode reset data or when power is up, and a test mode selection signal generator configured to receive the test information data provided from the test mode maintenance signal generator and the test mode maintenance signal and to generate a specific test mode selection signal, the activation of the specific test mode selection signal being controlled by the second reset pulse.Type: ApplicationFiled: December 18, 2007Publication date: November 13, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Young Do Hur
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Publication number: 20080140334Abstract: A semiconductor package includes an input pin that receives a first signal from the outside of the semiconductor package, a pad that is coupled to the input pin, and a test mode driving circuit that receives the first signal from the pad and outputs a plurality of test mode signals to drive a test apparatus in a semiconductor chip.Type: ApplicationFiled: July 17, 2007Publication date: June 12, 2008Applicant: Hynix Semiconductor Inc.Inventor: Young Do Hur
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Publication number: 20070297547Abstract: A first shifting unit outputs first shifting signals using at least one of periodic signals. A control signal generating unit outputs multiplexing control signals using an inverted clock signal; a second shifting unit that outputs second shifting signals using the at least one of periodic signals. A correcting unit outputs correction signals having an intermediate phase between the phase of the first shifting signals and the phase of the second shifting signals on the basis of a bias signal applied thereto. A combination unit combines the first shifting signals and the correction signals to output combined signals. A multiplexing unit selectively outputs the combined signals on the basis of multiplexing control signals.Type: ApplicationFiled: December 29, 2006Publication date: December 27, 2007Applicant: Hynix Semiconductor Inc.Inventor: Young Do Hur
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Patent number: 7212046Abstract: In a power-up signal generating device, a power-up signal is activated at a certain level of the power supply voltage VDD by adjusting the turn-on resistance value of the MOS transistor so that the chip reliability can be improved. The power-up signal generating device comprises a reference voltage generating unit, a bias level adjusting unit, a bias signal generating unit and a signal outputting unit. The reference voltage generating unit generates a reference voltage. The bias level adjusting unit receives the reference voltage as an input for controlling a voltage level of a bias signal in a constant level. The bias signal generating unit generates the bias signal under control of the bias level adjusting unit. The signal outputting unit outputs a power-up signal depending on the voltage level of the bias signal.Type: GrantFiled: June 23, 2004Date of Patent: May 1, 2007Assignee: Hynix Semiconductor Inc.Inventor: Young-Do Hur
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Publication number: 20070070672Abstract: A semiconductor device includes a first internal voltage generator generating an internal voltage using a first external power supply voltage in a normal mode; a second internal voltage generator generating the internal voltage using a second external power supply voltage supplied through a no connection (N/C) pin in a test mode; an internal operation circuit performing a target operation with the internal voltage generated at one of the first internal voltage generator and the second internal voltage generator; and a data output buffer outputting an output data in response to the target operation by the internal operation circuit through a data input/output pad in one of the normal mode and the test mode.Type: ApplicationFiled: September 28, 2006Publication date: March 29, 2007Inventor: Young-Do Hur
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Publication number: 20050093529Abstract: In a power-up signal generating device, a power-up signal is activated at a certain level of the power supply voltage VDD by adjusting the turn-on resistance value of the MOS transistor so that the chip reliability can be improved. The power-up signal generating device comprises a reference voltage generating unit, a bias level adjusting unit, a bias signal generating unit and a signal outputting unit. The reference voltage generating unit generates a reference voltage. The bias level adjusting unit receives the reference voltage as an input for controlling a voltage level of a bias signal in a constant level. The bias signal generating unit generates the bias signal under control of the bias level adjusting unit. The signal outputting unit outputs a power-up signal depending on the voltage level of the bias signal.Type: ApplicationFiled: June 23, 2004Publication date: May 5, 2005Inventor: Young-Do Hur
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Patent number: 6744687Abstract: Disclosed are a semiconductor memory device with a mode register that prevents the semiconductor device from undesirably entering into a deep power down mode during the beginning of a power up and a method for controlling a deep power down mode therein. An internal power supply voltage generator generates an internal power supply voltage of the semiconductor memory device. A clock buffer buffers external clock and clock enable signals to generate internal clock and clock enable signals. A command decoder generates an intermediate deep power down mode entry signal or a mode register setting signal. A mode register setting latch circuit latches the mode register setting signal from the command decoder. A deep power down mode controller generates a final deep power down mode entry signal. A semiconductor memory device is accordingly prevented from undesirably entering into a deep power down mode during beginning of a power up.Type: GrantFiled: December 30, 2002Date of Patent: June 1, 2004Assignee: Hynix Semiconductor Inc.Inventors: Kie Bong Koo, Young Do Hur
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Publication number: 20030210600Abstract: Disclosed are a semiconductor memory device with a mode register that prevents the semiconductor device from undesirably entering into a deep power down mode during the beginning of a power up and a method for controlling a deep power down mode therein. An internal power supply voltage generator generates an internal power supply voltage of the semiconductor memory device. A clock buffer buffers external clock and clock enable signals to generate internal clock and clock enable signals. A command decoder generates an intermediate deep power down mode entry signal or a mode register setting signal. A mode register setting latch circuit latches the mode register setting signal from the command decoder. A deep power down mode controller generates a final deep power down mode entry signal. A semiconductor memory device is accordingly prevented from undesirably entering into a deep power down mode during beginning of a power up.Type: ApplicationFiled: December 30, 2002Publication date: November 13, 2003Inventors: Kie Bong Koo, Young Do Hur
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Patent number: 6639854Abstract: A semiconductor memory device having a redundancy circuit, includes a normal memory cell array unit, a redundancy memory cell array unit for recovering defective cells of the normal memory cell array unit, and a memory driving unit for operating the normal memory cell adjacent to the redundancy memory cell array unit immediately after a word line move time ‘tcycle’ is elasped by using address data.Type: GrantFiled: December 18, 2001Date of Patent: October 28, 2003Assignee: Hynix Semiconductor Inc.Inventors: Young Do Hur, Jong Chern Lee
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Patent number: 6545531Abstract: A power voltage driver circuit includes: a constant voltage generating unit for generating a first constant voltage and a second constant voltage; a clock input buffer unit using an internal step-down voltage as a power source; a control unit for receiving an operation control signal indicating the low power operation mode; a voltage comparing unit controlled in response to the output signal from the control unit, for stopping the operation in the low power operation mode, and receiving the first and second constant voltages in the other operation modes, and generating a signal by comparing and amplifying the first and second constant voltages with a reference voltage; and a driver unit controlled in response to the output signal from the control unit.Type: GrantFiled: December 28, 2001Date of Patent: April 8, 2003Assignee: Hynix Semiconductor Inc.Inventor: Young Do Hur
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Patent number: 6518831Abstract: A boosting circuit for a high voltage operation in a semiconductor memory device for preventing a transistor of a high voltage pump circuit from being destroyed due to an excessive bootstrap voltage in a pumping operation, by controlling the operation of the high voltage pump circuit according to a signal detecting that the bootstrap voltage of the high voltage pump circuit has increased above a predetermined level.Type: GrantFiled: December 6, 2001Date of Patent: February 11, 2003Assignee: Hynix Semiconductor Inc.Inventors: Young Do Hur, Seung Han Ok