Patents by Inventor Young-Eun Lee

Young-Eun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8213086
    Abstract: A coating composition for antireflection that includes a low refraction-thermosetting resin having a refractive index of 1.2 to 1.45, a high refraction-ultraviolet curable resin having a refractive index of 1.46 to 2, and an ultraviolet absorber; an antireflection film manufactured using the coating composition; and a method of manufacturing the antireflection film. The antireflection film has excellent abrasion resistance and antireflection characteristic. Further, since the antireflection film can be manufactured in one coating process, it is possible to reduce manufacturing cost.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: July 3, 2012
    Assignee: LG Chem, Ltd.
    Inventors: Yeong-Rae Chang, Young-Jun Hong, Young-Eun Lee, Tae-Su Kim, Hyun-Woo Shin, Bu-Gon Shin
  • Publication number: 20120131595
    Abstract: Disclosed herein is a parallel collision detection method using load balancing in order to detect collision between two objects of a polygon soup. The parallel collision detection method is processed in parallel using a plurality of threads. The parallel collision detection method includes traversing a Bounding Volume Traversal Tree (BVTT) using Bounding Volume Hierarchies (BVHs) related to the polygon soup in a depth first search manner or a width first search manner; recursively traversing the children node of an internal node (a parent node) when a currently traversed node is the internal node and two Boundary Volumes (BVs) in the corresponding node overlap, and stopping to traverse the node when the currently traversed node is the internal node and two Boundary Volumes (BVs) do not overlap; and storing collision primitives in a leaf node when the currently traversed node is the leaf node and collision primitives in the leaf node overlap.
    Type: Application
    Filed: May 24, 2011
    Publication date: May 24, 2012
    Applicant: EWHA UNIVERSITY-INDUSTRY COLLABORATION FOUNDATION
    Inventors: Young Jun KIM, Young Eun Lee
  • Patent number: 8179499
    Abstract: A liquid crystal display device capable of reducing a time delay in lighting of the liquid crystal display device includes a liquid crystal panel, at least one fluorescent lamps disposed below the liquid crystal panel, formed as a cylindrical shape having a central axis and supplying light to the liquid crystal panel, and at least one auxiliary optical source disposed to face the liquid crystal panel while having the central axis therebetween and supplying light to the fluorescent lamps.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: May 15, 2012
    Assignee: LG Display Co., Ltd.
    Inventor: Young-Eun Lee
  • Patent number: 8110249
    Abstract: An antireflective coating composition includes a photopolymerizable acrylate monomer (C1); a particle-type metal fluoride (C2) with a refractive index of 1.40 or less; a photopolymerization initiator (C3); and at least one liquid dispersion-enhancing chelating agent (C4) selected from the group consisting of Mg(CF3COO)2, Na(CF3COO), K(CF3COO), Ca(CF3COO)2, Mg(CF2COCHCOCF3)2 and Na(CF2COCHCOCF3). This composition ensures good mechanical strength, excellent adhesion to a substrate, short curing time by UV curing, prevention of dust attachment, good erasure of stain, good dust removal and good scratch resistance, so it is usefully for making an antireflective coating film of a display.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: February 7, 2012
    Assignee: LG Chem, Ltd.
    Inventors: Joon-Koo Kang, Mi-Young Han, Young-Eun Lee, Young-Jun Hong, Yeong-Rae Chang
  • Publication number: 20110300704
    Abstract: A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
    Type: Application
    Filed: August 8, 2011
    Publication date: December 8, 2011
    Inventors: Yong-Hoon Son, Yu-Gyun Shin, Jong-Wook Lee, Sun-Ghil Lee, In-Soo Jung, Young-Eun Lee, Deok-Hyung Lee
  • Publication number: 20110265608
    Abstract: Disclosed is a method of producing ultra low phosphorus and carbon ferromanganese having 0.1 wt % or less carbon and 0.03 wt % or less phosphorus. The method includes preparing low carbon silicomanganese having low phosphorus content, preparing molten manganese slag, subjecting the molten manganese slag and the low carbon silicomanganese having low phosphorus content to primary mixing and stirring at a ratio of 70˜72:28˜30 in a ladle, thus producing a metal melt and slag, and subjecting the metal melt separated from the above slag and the molten manganese slag identical to that used in the primary mixing and stirring to secondary mixing and stirring, thus producing slag and a metal melt including 91˜93 wt % manganese, 0.60˜0.85 wt % silicon, 0.05˜0.10 wt % carbon and 0.015˜0.02 wt % phosphorus.
    Type: Application
    Filed: November 19, 2008
    Publication date: November 3, 2011
    Inventors: Dong-Shik Min, Chan-Soo Park, Young-Eun Lee, Hai-Chang Cho, Kwang-Jung Lee, Sung-Hwan Hong
  • Patent number: 7998851
    Abstract: A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: August 16, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-Hoon Son, Yu-Gyun Shin, Jong-Wook Lee, Sun-Ghil Lee, In-Soo Jung, Young-Eun Lee, Deok-Hyung Lee
  • Patent number: 7880715
    Abstract: A display device and an inverter therefor are disclosed. The inverter has a main circuit board having a plurality of first circuit patterns and a plurality of second circuit patterns formed on a first side thereof, and a sub circuit board having first connecting patterns corresponding to the plurality of first circuit patterns formed on one side of the sub circuit board and second connecting patterns corresponding to the plurality of second circuit patterns formed on a second side thereof. The plurality of first circuit patterns are coupled with each other through the first connecting patterns, and the plurality of second circuit patterns are coupled with each other through the second connecting patterns. Thus, the present invention provides an inverter and a display device having the same, which are capable of being manufactured at a low production cost.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: February 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eui-dong Hwang, Young-eun Lee, Young-sup Kwon, Dal-jung Kwon
  • Patent number: 7799648
    Abstract: A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
    Type: Grant
    Filed: June 4, 2009
    Date of Patent: September 21, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Ghil Lee, Young-Pil Kim, Yu-Gyun Shin, Jong-Wook Lee, Young-Eun Lee
  • Publication number: 20100159689
    Abstract: A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
    Type: Application
    Filed: March 2, 2010
    Publication date: June 24, 2010
    Inventors: Yong-Hoon Son, Yu-Gyun Shin, Jong-Wook Lee, Sun-Ghil Lee, In-Soo Jung, Young-Eun Lee, Deok-Hyung Lee
  • Publication number: 20100076109
    Abstract: An antireflective coating composition includes a photopolymerizable acrylate monomer (C1); a particle-type metal fluoride (C2) with a refractive index of 1.40 or less; a photopolymerization initiator (C3); and at least one liquid dispersion-enhancing chelating agent (C4) selected from the group consisting of Mg(CF3COO)2, Na(CF3COO), K(CF3COO), Ca(CF3COO)2, Mg(CF2COCHCOCF3)2 and Na(CF2COCHCOCF3). This composition ensures good mechanical strength, excellent adhesion to a substrate, short curing time by UV curing, prevention of dust attachment, good erasure of stain, good dust removal and good scratch resistance, so it is usefully for making an antireflective coating film of a display.
    Type: Application
    Filed: July 6, 2007
    Publication date: March 25, 2010
    Applicant: LG CHEM, LTD.
    Inventors: Joon-Koo Kang, Mi-Young Han, Young-Eun Lee, Young-Jun Hong, Yeong-Rae Chang
  • Publication number: 20090296219
    Abstract: The present invention provides a coating composition for antireflection that includes a low refraction-thermosetting resin having a refractive index of 1.2 to 1.45, a high refraction-ultraviolet curable resin having a refractive index of 1.46 to 2, and an ultraviolet absorber; an antireflection film manufactured using the coating composition; and a method of manufacturing the antireflection film. The antireflection film according to the present invention has excellent abrasion resistance and antireflection characteristic. Further, since the antireflection film can be manufactured in one coating process, it is possible to reduce manufacturing cost.
    Type: Application
    Filed: December 28, 2007
    Publication date: December 3, 2009
    Inventors: Yeong-Rae Chang, Young-Jun Hong, Young-Eun Lee, Tae-Su Kim, Hyun-Woo Shin, Bu-Gon Shin
  • Publication number: 20090285993
    Abstract: An antireflective coating composition includes a hydrolytic condensate (C1) of alkoxy silane (C11) and fluoric alkoxy silane (C12); a particle-type metal fluoride (C2) with a refractive index of 1.40 or less; and a liquid dispersion-enhancing chelating agent (C3). A coating film to which the above composition is applied controls refractive index, surface energy, film strength and so on, so it ensures excellent antireflective characteristic, excellent scratch resistance, good erasure of liquid stains such as fingerprints, and particularly excellent dust removal, so it may be usefully applied to an outermost layer of a front surface of a display regardless of kind of a display substrate or presence of an additional coating layer.
    Type: Application
    Filed: July 6, 2007
    Publication date: November 19, 2009
    Inventors: Joon-Koo Kang, Mi-Young Han, Young-Eun Lee, Young-Jun Hong, Yeong-Rae Chang
  • Publication number: 20090239348
    Abstract: A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
    Type: Application
    Filed: June 4, 2009
    Publication date: September 24, 2009
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-Ghil Lee, Young-Pil Kim, Yu-Gyun Shin, Jong-Wook Lee, Young-Eun Lee
  • Patent number: 7557388
    Abstract: A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: July 7, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-Ghil Lee, Young-Pil Kim, Yu-Gyun Shin, Jong-Wook Lee, Young-Eun Lee
  • Patent number: 7524210
    Abstract: A capacitive connector for a backlight unit having a light source including: a first conductive layer covering an end portion of the light source; an insulation layer covering an external surface of the first conductive layer; and a second conductive layer separated from the first conductive layer with the insulation layer interposed therebetween.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: April 28, 2009
    Assignee: LG Display Co., Ltd.
    Inventors: Young-Eun Lee, Seung-Hyun Lee
  • Publication number: 20080308845
    Abstract: Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.
    Type: Application
    Filed: August 21, 2008
    Publication date: December 18, 2008
    Inventors: Sung-Min Kim, Kyoung-Hwan Yeo, In-Soo Jung, Si-Young Choi, Dong-Won Kim, Yong-Hoon Son, Young-Eun Lee, Byeong-Chan Lee, Jong-Wook Lee
  • Publication number: 20080256476
    Abstract: Provided are a copying apparatus and a user interface method for the same. The user interface method includes displaying a first region which includes information on an original document, and displaying a second region which includes information on virtual copy paper; changing the display of the second region in accordance with an input setting instruction; and when a copy instruction is input, copying the original document in accordance with the display of the second region. According to the present invention, an intuitive interface which even inexperienced users can easily use may be implemented.
    Type: Application
    Filed: November 5, 2007
    Publication date: October 16, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon-kyu SEO, Hyun-ki KIM, Jung-won LEE, Young-eun LEE, Hee-jeong BAE
  • Patent number: 7429504
    Abstract: Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.
    Type: Grant
    Filed: March 15, 2005
    Date of Patent: September 30, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Min Kim, Kyoung-Hwan Yeo, In-Soo Jung, Si-Young Choi, Dong-Won Kim, Yong-Hoon Son, Young-Eun Lee, Byeong-Chan Lee, Jong-Wook Lee
  • Patent number: D578132
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: October 7, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young Eun Lee