Patents by Inventor Young-Eun Lee

Young-Eun Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080231775
    Abstract: A liquid crystal display device capable of reducing a time delay in lighting of the liquid crystal display device includes a liquid crystal panel, at least one fluorescent lamps disposed below the liquid crystal panel, formed as a cylindrical shape having a central axis and supplying light to the liquid crystal panel, and at least one auxiliary optical source disposed to face the liquid crystal panel while having the central axis therebetween and supplying light to the fluorescent lamps.
    Type: Application
    Filed: December 28, 2007
    Publication date: September 25, 2008
    Applicant: LG.PHILIPS LCD CO., LTD.
    Inventor: Young-Eun Lee
  • Publication number: 20080214024
    Abstract: A capacitive connector for a backlight unit having a light source including: a first conductive layer covering an end portion of the light source; an insulation layer covering an external surface of the first conductive layer; and a second conductive layer separated from the first conductive layer with the insulation layer interposed therebetween.
    Type: Application
    Filed: December 28, 2007
    Publication date: September 4, 2008
    Inventors: Young-Eun Lee, Seung-Hyun Lee
  • Patent number: 7393700
    Abstract: Methods of etching a semiconductor substrate may include providing a first gas that is chemically reactive with respect to the semiconductor substrate, and while providing the first gas, providing a second gas different than the first gas. More particularly, a molecule of the second gas may include a hydrogen atom, and the second gas may lower a temperature at which the first gas chemically reacts with the semiconductor substrate. The mixture of the first and second gases may be provided adjacent the semiconductor substrate to etch the semiconductor substrate.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: July 1, 2008
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Sun-Ghil Lee, Yu-Gyun Shin, Jong-Wook Lee, Deok-Hyung Lee, In-Soo Jung, Young-Eun Lee
  • Patent number: 7315063
    Abstract: A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a source/drain region formed in relation to an epitaxial layer formed in a recess region.
    Type: Grant
    Filed: February 28, 2006
    Date of Patent: January 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-eun Lee, Seong-ghil Lee, Yu-gyun Shin, Jong-wook Lee, Young-pil Kim
  • Publication number: 20070234166
    Abstract: A display device and an inverter therefor are disclosed. The inverter has a main circuit board having a plurality of first circuit patterns and a plurality of second circuit patterns formed on a first side thereof, and a sub circuit board having first connecting patterns corresponding to the plurality of first circuit patterns formed on one side of the sub circuit board and second connecting patterns corresponding to the plurality of second circuit patterns formed on a second side thereof. The plurality of first circuit patterns are coupled with each other through the first connecting patterns, and the plurality of second circuit patterns are coupled with each other through the second connecting patterns. Thus, the present invention provides an inverter and a display device having the same, which are capable of being manufactured at a low production cost.
    Type: Application
    Filed: February 20, 2007
    Publication date: October 4, 2007
    Inventors: Eui-dong Hwang, Young-eun Lee, Young-sup Kwon, Dal-jung Kwon
  • Patent number: 7204877
    Abstract: The present invention relates to a coating composition for forming an anti-reflective coating layer for a display device, comprising a fluorinated silane with low surface tension, a conductive polymer with antistatic properties, water, and a solvent. Thus, the coating film of the present invention prepared by coating the composition has high anti-reflection, excellent stain resistance to liquid-phase stains such as fingerprints and the solid-phase stains such as dust by controlling the refractive index, surface energy, and conductivity, and thus can be usefully applied to the outermost side of a display device, regardless of the type of substrates such as a Braun tube or a flat display film and the presence of other coating layers such as a hard coating layer and an anti-glare coating layer.
    Type: Grant
    Filed: April 13, 2005
    Date of Patent: April 17, 2007
    Assignee: LG Chem, Ltd.
    Inventors: Young-Eun Lee, Mi-Young Han, Yeong-Rae Chang, Jeong-Jin Hong, Sung-Hoon Jang
  • Publication number: 20060292783
    Abstract: A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a source/drain region formed in relation to an epitaxial layer formed in a recess region.
    Type: Application
    Filed: February 28, 2006
    Publication date: December 28, 2006
    Inventors: Young-eun Lee, Seong-ghil Lee, Yu-gyun Shin, Jong-wook Lee, Young-pil Kim
  • Publication number: 20060283380
    Abstract: A semiconductor device formed on a strained silicon layer and a method of manufacturing such a semiconductor device are disclosed. In accordance with this invention, a first silicon germanium layer is formed on a single crystalline silicon substrate; a second silicon germanium layer is formed on the first silicon germanium layer, the second silicon germanium layer having a concentration of germanium in a range of about 1 percent by weight to about 15 percent by weight based on the total weight of the second silicon germanium layer; a strained silicon layer is formed on the second silicon germanium layer; an isolation layer is formed at a first portion of the strained silicon layer; a gate structure is formed on the strained silicon layer; and, source/drain regions are formed at second portions of the strained silicon layer adjacent to the gate structure to form a transistor.
    Type: Application
    Filed: April 5, 2006
    Publication date: December 21, 2006
    Inventors: Sun-Ghil Lee, Young-Pil Kim, Yu-Gyun Shin, Jong-Wook Lee, Young-Eun Lee
  • Publication number: 20060057821
    Abstract: Methods of etching a semiconductor substrate may include providing a first gas that is chemically reactive with respect to the semiconductor substrate, and while providing the first gas, providing a second gas different than the first gas. More particularly, a molecule of the second gas may include a hydrogen atom, and the second gas may lower a temperature at which the first gas chemically reacts with the semiconductor substrate. The mixture of the first and second gases may be provided adjacent the semiconductor substrate to etch the semiconductor substrate.
    Type: Application
    Filed: August 22, 2005
    Publication date: March 16, 2006
    Inventors: Sun-Ghil Lee, Yu-Gyun Shin, Jong-Wook Lee, Deok-Hyung Lee, In-Soo Jung, Young-Eun Lee
  • Publication number: 20050248035
    Abstract: A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.
    Type: Application
    Filed: March 29, 2005
    Publication date: November 10, 2005
    Inventors: Yong-Hoon Son, Yu-Gyun Shin, Jong-Wook Lee, Sun-Ghil Lee, In-Soo Jung, Young-Eun Lee, Deok-Hyung Lee
  • Publication number: 20050239933
    Abstract: The present invention relates to a coating composition for forming an anti-reflective coating layer for a display device, comprising a fluorinated silane with low surface tension, a conductive polymer with antistatic properties, water, and a solvent. Thus, the coating film of the present invention prepared by coating the composition has high anti-reflection, excellent stain resistance to liquid-phase stains such as fingerprints and the solid-phase stains such as dust by controlling the refractive index, surface energy, and conductivity, and thus can be usefully applied to the outermost side of a display device, regardless of the type of substrates such as a Braun tube or a flat display film and the presence of other coating layers such as a hard coating layer and an anti-glare coating layer.
    Type: Application
    Filed: April 13, 2005
    Publication date: October 27, 2005
    Inventors: Young-Eun Lee, Mi-Young Han, Yeong-Rae Chang, Jeong-Jin Hong, Sung-Hoon Jang
  • Publication number: 20050218395
    Abstract: Embodiments of the present invention include heterogeneous substrates, integrated circuits formed on such heterogeneous substrates, and methods of forming such substrates and integrated circuits. The heterogeneous substrates according to certain embodiments of the present invention include a first Group IV semiconductor layer (e.g., silicon), a second Group IV pattern (e.g., a silicon-germanium pattern) that includes a plurality of individual elements on the first Group IV semiconductor layer, and a third Group IV semiconductor layer (e.g., a silicon epitaxial layer) on the second Group IV pattern and on a plurality of exposed portions of the first Group IV semiconductor layer. The second Group IV pattern may be removed in embodiments of the present invention. In these and other embodiments of the present invention, the third Group IV semiconductor layer may be planarized.
    Type: Application
    Filed: March 15, 2005
    Publication date: October 6, 2005
    Inventors: Sung-Min Kim, Kyoung-Hwan Yeo, In-Soo Jung, Si-Young Choi, Dong-Won Kim, Yong-Hoon Son, Young-Eun Lee, Byeong-Chan Lee, Jong-Wook Lee
  • Patent number: D574390
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: August 5, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young Eun Lee
  • Patent number: D575299
    Type: Grant
    Filed: April 11, 2007
    Date of Patent: August 19, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young Eun Lee