Abstract: There is provided a probe card in contact with pads formed on a plurality of semiconductor dies on a wafer to test the semiconductor dies. The probe card includes a printed circuit board on which a plurality of pads are formed; a block plate having a plurality of grooves and attached to the printed circuit board; a plurality of sub-probe units equipped with a plurality of probe tips in contact with the pads of the semiconductor dies and detachably coupled to the plurality of grooves; and a plurality of interposer/space transformer units interposed between the sub-probe units and the printed circuit board and configured to electrically connect the probe tips to the pads of the printed circuit board and transform a pitch of the pads formed on the printed circuit to a pitch of the plurality of probe tips.

Abstract: A method of manufacturing a semiconductor device includes forming a lower metal layer, forming an interfacial oxide film on the lower metal layer, providing a metal precursor on the interfacial oxide film at a first pressure to adsorb the metal precursor into the interfacial oxide film, performing a first purge process at a second pressure to remove the unadsorbed metal precursor, the second pressure lower than the first pressure, providing an oxidizing gas at the first pressure to react with the adsorbed metal precursor, performing a second purge process at the second pressure to remove the unreacted oxidizing gas and form a dielectric film, and forming an upper metal layer on the dielectric film.

Abstract: A method of manufacturing a capacitor for a semiconductor device includes forming a lower electrode, forming a dielectric layer on the lower electrode, forming a first upper electrode on the dielectric layer, adsorbing an organic silicon source onto a surface of the first upper electrode, and forming a second upper electrode on the first upper electrode onto which the organic silicon source is adsorbed. Related devices and fabrication methods are also discussed.

Abstract: A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

Abstract: A battery package is disclosed. The battery package has a battery module formed by stacking a plurality of pouch-type battery cells, a cover disposed on an outside of the battery module, an air communication channel fluidly connecting the battery module and an area outside of the cover, and a blower fluidly connected to the battery module.

Abstract: An electronic equipment chamber is disclosed. The electronic equipment chamber has an electronic equipment chamber board on which at least one electronic component among a current sensor, a relay, and a fuse is disposed, a controller located in a center of the electronic equipment chamber board, the controller electrically connected to the electronic component and configured to control the electronic component, and a plurality of busbars electrically connected to the electronic component and disposed along an outer edge of the electronic equipment chamber board, the plurality of busbars spaced apart from the controller.

Abstract: A method of fabricating semiconductor devices may include forming a mold structure on a lower layer, the mold structure including an etch stop layer doped at a first impurity concentration, a lower mold layer doped at a second impurity concentration, and an undoped upper mold layer. The method may include forming a trench exposing the lower layer in the mold structure using dry etching, extending a width of the trench in the etch stop layer using wet etching, and forming a first conductive pattern in the extended width trench, wherein an etch rate of the etch stop layer with respect to the dry etching may be smaller than an etch rate of the lower mold layer with respect to the dry etching, and an etch rate of the etch stop layer with respect to the wet etching may be proportional to the first impurity concentration.

Abstract: A method of manufacturing a capacitor for a semiconductor device includes forming a lower electrode, forming a dielectric layer on the lower electrode, forming a first upper electrode on the dielectric layer, adsorbing an organic silicon source onto a surface of the first upper electrode, and forming a second upper electrode on the first upper electrode onto which the organic silicon source is adsorbed. Related devices and fabrication methods are also discussed.

Abstract: A battery module includes battery cells arranged side-by-side in a stacked configuration, the battery cells having positive and negative cell terminals. Buss bars are electrically connected to corresponding cell terminals to electrically connect adjacent battery cells. A battery cover coupled to the battery cells. A module controller is held by the battery cover and is electrically connected to the buss bars to monitor a voltage of the corresponding buss bar.

Abstract: An electronic device may include a substrate, an oxide dielectric layer on the substrate, an interface layer on the oxide dielectric layer, and an electrode on the interface layer. The oxide dielectric layer may include an aluminum oxide layer between first and second zirconium oxide layers. The interface layer may have a first formation enthalpy, and the oxide dielectric layer may be between the substrate and the interface layer. The electrode may have a second formation enthalpy higher than the first formation enthalpy, and the interface layer may be between the oxide dielectric layer and the electrode.

Abstract: A power connection box is disclosed for a hybrid vehicle and includes a current supply member and a lead line installation member. The current supply member has a first main relay, a second main relay, a bus bar, and a preliminary relay. The bus bar is connected to the first main relay and has a side connected to a battery and an opposite side connected to an inverter. The preliminary relay is positioned between the first main relay and the bus bar connected to the first main relay. The lead line installation member has a plurality of lead lines connected to the first main relay, the second main relay, and the preliminary relay.

Abstract: There is provided a probe card in contact with pads formed on a plurality of semiconductor dies on a wafer to test the semiconductor dies. The probe card includes a printed circuit board on which a plurality of pads are formed; a block plate having a plurality of grooves and attached to the printed circuit board; a plurality of sub-probe units equipped with a plurality of probe tips in contact with the pads of the semiconductor dies and detachably coupled to the plurality of grooves; and a plurality of interposer/space transformer units interposed between the sub-probe units and the printed circuit board and configured to electrically connect the probe tips to the pads of the printed circuit board and transform a pitch of the pads formed on the printed circuit to a pitch of the plurality of probe tips.

Abstract: A battery module includes battery cells arranged side-by-side in a stacked configuration, the battery cells having positive and negative cell terminals. Buss bars are electrically connected to corresponding cell terminals to electrically connect adjacent battery cells. A battery cover coupled to the battery cells. A module controller is held by the battery cover and is electrically connected to the buss bars to monitor a voltage of the corresponding buss bar.

Abstract: Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current.

Abstract: The present invention relates to a combination connector for a vehicle that facilitates a connector assembling process in an in-line assembly line by integrating a connector which is a coupling part for wires extending to various electrical parts. Specifically, several connectors are coupled to one connector so as to be electrically connected to it, thereby concentrating the connector assembling processes in an in-line assembly line at one place and enhancing production yield and/or production rate.

Abstract: The present invention relates to a combination connector for a vehicle that facilitates a connector assembling process in an in-line assembly line by integrating a connector which is a coupling part for wires extending to various electrical parts. Specifically, several connectors are coupled to one connector so as to be electrically connected to it, thereby concentrating the connector assembling processes in an in-line assembly line at one place and enhancing production yield and/or production rate.

Abstract: Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process.

Abstract: Methods of forming conductive patterns include forming a conductive layer including a metal element on a substrate. The conductive layer is partially etched to generate a residue including an oxide of the metal element and to form a plurality of separately formed conductive layer patterns. A cleaning gas is inflowed onto the substrate including the conductive layer pattern. The metal compound is evaporated to remove the metal element contained in the residue and to form an insulating interface layer on the conductive layer pattern and a surface portion of the substrate through a reaction of a portion of the cleaning gas and oxygen. The residue may be removed from the conductive layer pattern to suppress generation of a leakage current.

Abstract: In methods of manufacturing a semiconductor device, a plurality of gate structures spaced apart from each other and oxide layer patterns. A sputtering process using the oxide layer patterns as a sputtering target to connect the oxide layer patterns on the adjacent gate structures to each other is performed, so that a gap is formed between the gate structures. A volume of the gap is formed uniformly to have desired volume by controlling a thickness of the oxide layer patterns.

Abstract: A method of fabricating a floating trap type nonvolatile memory device includes forming a cell gate insulating layer on a semiconductor substrate, the cell gate insulating layer being comprised of a lower insulating layer, a charge storage layer and an upper insulating layer sequentially stacked; thermally annealing the cell gate insulating Layer at a temperature of approximately 810° C. to approximately 1370° C.; and forming a gate electrode on the thermally annealed cell gate insulating layer.