Patents by Inventor Young Geun Park

Young Geun Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060166476
    Abstract: In a method of manufacturing a dielectric structure, after a first dielectric layer is formed on a substrate by using a metal oxide doped with silicon, the substrate is placed on a susceptor of a chamber. By treating the first dielectric layer with a plasma in controlling a voltage difference between the susceptor and a ground, a second dielectric layer is formed on the first dielectric layer. The second dielectric layer including a metal oxynitride doped with silicon having enough content of nitrogen is formed on the first dielectric layer. Therefore, dielectric properties of the dielectric structure comprising the first and the second dielectric layers can be improved and a leakage current can be greatly decreased. By adapting the dielectric structure to a gate insulation layer and/or to a dielectric layer of a capacitor or of a non-volatile semiconductor memory device, capacitances and electrical properties can be improved.
    Type: Application
    Filed: January 25, 2006
    Publication date: July 27, 2006
    Inventors: Jong-Cheol Lee, Sung-Tae Kim, Young-Sun Kim, Cha-Young Yoo, Gab-Jin Nam, Young-Geun Park, Jae-Hyoung Choi, Jae-Hyun Yeo, Ha-Jin Lim, Yun-Seok Kim
  • Patent number: 7061101
    Abstract: Carrier module including a carrier module body for seating a semiconductor device on an underside thereof, having a pass through hole from an upper part to the underside the semiconductor device is seated thereon, a housing over the carrier module body, a supplementary housing fitted in a lower part of the housing to be movable in up/down directions, for elastic contact with the carrier module body by a first elastic member fitted inside of the housing, a vacuum tube in the supplementary housing so as to be in communication with the pass through hole in the carrier module body, at least one pair of latches in a lower part of the carrier module body to move apart or close in an outer or inner side, for holding or releasing the semiconductor device seated on the carrier module body, a latch button fitted in an upper part of the carrier module body so as to be movable in up/down directions, and coupled to the latch with a connection pin for moving in up/down directions by an external force, to making the latch t
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: June 13, 2006
    Assignee: Mirae Corporation
    Inventors: Chul Ho Ham, Byoung Dae Lee, Ho Keun Song, Young Geun Park
  • Publication number: 20060072281
    Abstract: The present invention can provide methods of forming a layer including lanthanum by utilizing a lanthanum precursor existing in a liquid phase at a room temperature. The present invention can further provide methods of forming layers including lanthanum on objects and methods of manufacturing a capacitor.
    Type: Application
    Filed: August 4, 2005
    Publication date: April 6, 2006
    Inventors: Gab-Jin Nam, Young-Geun Park, Young-Sun Kim, Han-Mei Choi, Seung-Hwan Lee, Ki-Yeon Park, Cha-Young You
  • Publication number: 20060073627
    Abstract: A method for fabricating a probe for a scanning probe microscope, wherein the probe includes a mounting block, a cantilever and a tip, includes the steps of: forming a first mask to define a pattern for the tip and a second mask to define a pattern for the cantilever on an SOI wafer having a handle layer containing {100} single-crystalline silicon, an insulating layer and a device layer containing {111} single-crystalline silicon; etching the device layer by using the first and the second masks; forming a sidewall passivation layer on the device layer; etching the device layer by using the first mask to form the tip; etching the handle layer by using a third mask to define a pattern for the mounting block. By using the method, a probe made of {111} single-crystalline silicon can be fabricated with high yield.
    Type: Application
    Filed: March 31, 2004
    Publication date: April 6, 2006
    Applicant: M2N INC.
    Inventors: Young-Geun Park, Kyu-Ho Hwang
  • Publication number: 20060017080
    Abstract: The field-effect transistor includes: a ferromagnetic layer, having a film thickness of 50 nm or less, which is made of a Ba—Mn oxide showing ferromagnetism at 0° C. or higher; a dielectric layer made of a dielectric material or a ferroelectric material, and the ferromagnetic layer and the dielectric layer are bonded to each other. Thus, it is possible to control the magnetism, the electricity transport property, and/or the magnetic resistivity effect at 0° C. or higher.
    Type: Application
    Filed: September 4, 2003
    Publication date: January 26, 2006
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Hidekazu Tanaka, Tomoji Kawai, Teruo Kanki, Young- Geun Park
  • Publication number: 20050212026
    Abstract: Trench capacitors that have insulating layer collars in undercut regions and methods of fabricating such trench capacitors are provided. Some methods of fabricating a trench capacitor include forming a first layer on a substrate. A second layer is formed on the first layer opposite to the substrate. A mask is formed that has an opening on top of the first and second layers. A first trench is formed by removing a portion of the first and second layers through the opening in the mask. A portion of the first layer under the second layer is removed to form an undercut region under the second layer. An insulating layer collar is formed in the undercut region under the second layer. A second trench is formed that extends from the first trench by removing a portion of the substrate through the opening in the mask. A buried plate is formed in the substrate along the second trench. A dielectric layer is formed on an inner wall and bottom of the second trench.
    Type: Application
    Filed: January 18, 2005
    Publication date: September 29, 2005
    Inventors: Suk-jin Chung, Seung-hwan Lee, Sung-tae Kim, Young-sun Kim, Jae-soon Lim, Young-geun Park
  • Publication number: 20050208718
    Abstract: Methods for forming a capacitor using an atomic layer deposition process include providing a reactant including an aluminum precursor onto a substrate to chemisorb a portion of the reactant to a surface of the substrate. The substrate has an underlying structure including a lower electrode. An ammonia (NH3) plasma is provided onto the substrate to form a dielectric layer including aluminum nitride on the substrate including the lower electrode. An upper electrode is formed on the dielectric layer.
    Type: Application
    Filed: February 24, 2005
    Publication date: September 22, 2005
    Inventors: Jae-Soon Lim, Sung-Tae Kim, Young-Sun Kim, Young-Geun Park, Suk-Jin Chung, Seung-Hwan Lee
  • Patent number: 6873169
    Abstract: Carrier module for a semiconductor device test handler including a carrier module body, a device seating part in an underside part of the carrier module body, at least one pair of first latches at opposite sides of the device seating part arranged opposite to, and movable away from, or close to, each other, for holding, or releasing opposite side parts of the semiconductor device seated on the device seating part, at least one pair of second latches rotatably fitted on opposite sides of the first latch, for holding an underside part of the semiconductor device seated on the device seating part, and releasing the semiconductor device interlocked with a releasing action of the first latch, a latch button fitted in an upper part of the carrier module to move in up/down directions and coupled to one end of the first latch, for moving up and down to make the first latch to move, and a first elastic member, and a second elastic member for elastic supporting of the first latch, and the second latch, thereby securely
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: March 29, 2005
    Assignee: Mirae Corporation
    Inventors: Chul Ho Ham, Byoung Dae Lee, Ho Keun Song, Young Geun Park
  • Publication number: 20040124845
    Abstract: A device for compensating for heat generation in a modular IC test handler is provided which includes at least one supporting member positioned adjacent to a press unit of the handler, and having a cooling fluid flow passage formed therein for flow of cooling fluid, and a plurality of cooling fluid spraying units for spraying the cooling fluid supplied through the cooling fluid flow passage toward faces of modular ICs in an oblique direction from a position between adjacent push bars of the press unit, thereby spraying cooling fluid directly onto ICs attached to a surface of modular ICs during testing and enhancing an efficiency of heat compensation.
    Type: Application
    Filed: September 9, 2003
    Publication date: July 1, 2004
    Applicant: Mirae Corporation
    Inventors: Chan Ho Park, Hyun Joo Hwang, Jae Bong Seo, Young Geun Park, Ho Keun Song
  • Patent number: 6153003
    Abstract: A simple method of preparing a homogeneous cellulose solution is disclosed, which comprises the steps of (a) preparing fibrillar cellulose powder; (b) injecting a molten liquid tertiary amine oxide solvent into a twin screw extruder; (c) feeding the cellulose powder of step (a) into a section of the twin screw extruder where the molten liquid tertiary amine oxide solvent fed in step (b) produces a well swollen paste with the cellulose powder fed in step (c); (d) dissolving the well swollen cellulose paste in the following melting sections in the twin screw extruder; and (e) stabilizing the solution obtained in step (d) in a storage tank.
    Type: Grant
    Filed: February 10, 1999
    Date of Patent: November 28, 2000
    Assignees: Korea Institute of Science and Technology, Hanil Synthetic Fiber Co., Ltd.
    Inventors: Wha Seop Lee, Byoung Chul Kim, Seong Mu Jo, Jong Su Park, Seong Joo Lee, Young Geun Park, Seung Lak Lee, Young Se Oh