Abstract: The present invention discloses a semiconductor memory device and a method of generating a block selection signal for the semiconductor memory device. The semiconductor memory device includes 2n groups comprised of m memory cell array blocks and each of the memory cell array blocks has (2k+a) word lines. The semiconductor memory device further includes a first block selection signal generating circuit for generating first block selection signals for selecting one group of the 2n groups by decoding a n-bit row address, a second block selection signal generating circuit for generating second block selection signals for selecting one memory cell array block in every group by decoding a l-bit row address, and a third block selection signal generating circuit for generating third block selection signals for selecting one memory cell array block out of (m×2n) memory cell array blocks by receiving the first block selection signals and the second block selection signals.

Abstract: The present invention discloses a semiconductor memory device and a method of generating a block selection signal for the semiconductor memory device. The semiconductor memory device includes 2n groups comprised of m memory cell array blocks and each of the memory cell array blocks has (2k+a) word lines. The semiconductor memory device further includes a first block selection signal generating circuit for generating first block selection signals for selecting one group of the 2n groups by decoding a n-bit row address, a second block selection signal generating circuit for generating second block selection signals for selecting one memory cell array block in every group by decoding a l-bit row address, and a third block selection signal generating circuit for generating third block selection signals for selecting one memory cell array block out of (m×2n) memory cell array blocks by receiving the first block selection signals and the second block selection signals.

Abstract: A semiconductor memory device with a bit line sense enable signal generating circuit is disclosed. The semiconductor memory device includes a word line selection signal generating circuit for generating a word line selection signal for selecting a word line; a delay circuit for generating a delayed signal by delaying a signal to the same extent of time period which is needed for the word line selection signal generating circuit to generate the word line selection signal; and a Schmitt trigger for generating a word line enable detecting signal by receiving an output signal from the delay circuit and that is connected to a power supply voltage which has the same voltage level as the voltage level used to enable the word line. The bit line sense enable signal generating circuit in the present invention occupies a relatively smaller layout area than that of conventional semiconductor memory devices.

Abstract: In a semiconductor memory device, a circuit for controlling a voltage level applied to a bit line isolation circuit preferably includes a memory cell connected between a cell bit line pair and a word line; a bit line pre-charge circuit; a sense amplifier bit line pre-charge circuit; a charge transfer circuit connected between the cell bit line pair and the sense amplifier bit line pair; a first sense amplifier circuit for amplifying a voltage of the sense amplifier bit line pair to a first voltage in response to a first control signal; and a second sense amplifier circuit for amplifying the voltage of the sense amplifier bit line pair to a second voltage in response to a second control signal. The combination of the two-stage sense amplifier ciruitry allows for the accurate determination of minimally-different logical voltage levels and minimized circuit area.

Abstract: A semiconductor integrated circuit includes a memory cell array, a read circuit that reads test data from the memory cell array, a parallel test control circuit, a bit organization address control circuit, and a parallel test circuit. The parallel test control circuit, in response to a wafer test flag signal, a package test flag signal, and a bank activation signal, generates a first control signal and a second control signal. The bit organization address control circuit, in response to the wafer test flag signal, the package test flag signal, the bank activation signal, and a bit organization information signal, generates a third control signal. The parallel test circuit, in response to the first and second control signals, determines whether all bits of the test data read have the same logic levels. The first, second, and third control signals determines where the test data are read from in the memory cell array.

Abstract: A semiconductor integrated circuit includes a memory cell array, a read circuit that reads test data from the memory cell array, a parallel test control circuit, a bit organization address control circuit, and a parallel test circuit. The parallel test control circuit, in response to a wafer test flag signal, a package test flag signal, and a bank activation signal, generates a first control signal and a second control signal. The bit organization address control circuit, in response to the wafer test flag signal, the package test flag signal, the bank activation signal, and a bit organization information signal, generates a third control signal. The parallel test circuit, in response to the first and second control signals, determines whether all bits of the test data read have the same logic levels. The first, second, and third control signals determines where the test data are read from in the memory cell array.