Abstract: Provided are a highly integrated semiconductor device with a silicide layer, which can secure a contact margin, and a method of manufacturing the highly integrated semiconductor device. The highly integrated semiconductor device includes a gate electrode formed on a semiconductor substrate. A source region and a drain region are formed in predetermined upper portions of the semiconductor substrate on two sides of the gate electrode such that each of the source region and the drain region includes a lightly doped drain (LDD) region and a heavily doped region. A silicide layer is formed on the gate electrode, the source region, and the drain region. The silicide layer has a sufficient thickness to function as an ohmic contact and is formed on the LDD region and the heavily doped region of each of the source region and the drain region.

Abstract: Provided are a more stable semiconductor integrated circuit device and a method of manufacturing the same.

Abstract: Electrically programmable integrated fuses are provided for low power applications. Integrated fuse devices have stacked structures with a polysilicon layer and a conductive layer formed on the polysilicon layer. The integrated fuses have structural features that enable the fuses to be reliably and efficiently programmed using low programming currents/voltages, while achieving consistency in fusing locations. For example, programming reliability and consistency is achieved by forming the conductive layers with varied thickness and forming the polysilicon layers with varied doping profiles, to provide more precise localized regions in which fusing events readily occur.

Abstract: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

Abstract: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

Abstract: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

Abstract: A transistor and method of formation thereof includes source and drain extension regions in which the diffusion of dopants into the channel region is mitigated or eliminated. This is accomplished, in part, by elevating the source and drain extension regions into the epitaxial layer formed on the underlying substrate. In doing so, the effective channel length is increased, while limiting dopant diffusion into the channel region. In this manner, performance characteristics of the transistor can be accurately determined by controlling the respective geometries (i.e. depths and widths) of the source/drain extension regions, the source/drain regions, the channel width and an optional trench formed in the underlying substrate. In the various embodiments, the source/drain regions and the source/drain extension regions may extend partially, or fully, through the epitaxial layer, or even into the underlying semiconductor substrate.

Abstract: The present invention provides a method for forming a circuit line which may be formed simply and economically by alleviating spread of an ink and exhibit excellent electric conductivity by having even height of the formed ink. The present invention further provides a conductive board with excellent high-dense electric conductivity including fine circuit lines. According to one embodiment of the present invention, a method for forming fine circuit lines comprises (a) treating at least one side of a circuit line pattern to be formed on a base substrate with an alkali metal hydroxide solution and (b) treating a hydrophobic ink in accordance to a circuit line pattern to be formed.

Abstract: Provided are a highly integrated semiconductor device with a silicide layer, which can secure a contact margin, and a method of manufacturing the highly integrated semiconductor device. The highly integrated semiconductor device includes a gate electrode formed on a semiconductor substrate. A source region and a drain region are formed in predetermined upper portions of the semiconductor substrate on two sides of the gate electrode such that each of the source region and the drain region includes a lightly doped drain (LDD) region and a heavily doped region. A silicide layer is formed on the gate electrode, the source region, and the drain region. The silicide layer has a sufficient thickness to function as an ohmic contact and is formed on the LDD region and the heavily doped region of each of the source region and the drain region.

Abstract: Provided are an improved structure for measuring gate misalignment and a measuring method thereof. The structure includes an active region and a device isolation region, a first gate group including a plurality of gates extending in one direction at one side of the active region, widths of the gates being the same with one another and lengths of the respective gates overlapping with the active region being different from one another, and a second gate group including a plurality of gates extending in one direction at the other side of the active region, widths of the gates being the same as one another and lengths of the respective gates overlapping with the active region being different from one another.

Abstract: A method and apparatus for manufacturing a nanocrystalline titanium alloy by performing an equal channel angular pressing process to a titanium alloy material, and a nanocrystalline titanium alloy manufactured using the method and apparatus. The method for manufacturing the nanocrystalline titanium alloy includes steps of preparing a titanium alloy material, and performing an equal channel angular pressing process on the titanium alloy material at an isothermal condition of 575° C. to 625° C. The nanocrystalline titanium alloy according to has a grain size of 300 nm.

Abstract: Provided are a highly integrated semiconductor device with a silicide layer, which can secure a contact margin, and a method of manufacturing the highly integrated semiconductor device. The highly integrated semiconductor device includes a gate electrode formed on a semiconductor substrate. A source region and a drain region are formed in predetermined upper portions of the semiconductor substrate on two sides of the gate electrode such that each of the source region and the drain region includes a lightly doped drain (LDD) region and a heavily doped region. A suicide layer is formed on the gate electrode, the source region, and the drain region. The silicide layer has a sufficient thickness to function as an ohmic contact and is formed on the LDD region and the heavily doped region of each of the source region and the drain region.

Abstract: Provided is a semiconductor device having an etch-resistant L-shaped spacer and a fabrication method thereof. The semiconductor device comprises a semiconductor substrate, a gate insulating layer formed on the semiconductor substrate, a gate electrode formed on the gate insulating layer, an L-shaped lower spacer conformally formed on sidewalls of the gate electrode and a portion of the substrate, an etch-resistant L-shaped spacer conformally formed on the L-shaped lower spacer, low-concentration source/drain regions aligned to sides of sidewall portions of the L-shaped lower spacer and formed within the substrate, and high-concentration source/drain regions aligned to sides of a bottom portions of the etch-resistant L-shaped spacer and formed within the substrate.

Abstract: MOSFETs with pocket regions are fabricated. A gate electrode layer is formed on a semiconductor substrate; and lightly doped drain regions are formed in the semiconductor substrate adjacent the gate electrode layer. A blocking pattern is formed on the semiconductor substrate where the gate electrode layer is formed. The blocking pattern is adjacent and spaced apart from the gate electrode layer a predetermined distance and exposes portions of the semiconductor substrate adjacent sidewalls of the gate electrode layer. Pocket regions are formed in the semiconductor substrate by implanting impurity ions using the gate electrode layer and the blocking pattern as an ion implantation mask.

Abstract: In a method of forming a CMOS device, first and second conductive structures are formed on a substrate. An insulation layer is formed on the substrate having the first and second conductive structures. The insulation layer is patterned to form an insulation layer pattern having a first portion on the first conductive structure and a second portion on the second conductive structure. The first portion has a compressive stress and functions as an etch stop layer. The second portion functions as an etch stop layer.

Abstract: The present invention provides a semiconductor transistor using an L-shaped spacer. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas.

Abstract: A method of fabricating a semiconductor device having an L-shaped spacer comprises forming a gate pattern on a transistor region of a semiconductor substrate. A disposable spacer is formed on an insulating layer of sidewalls of the gate pattern. Deeply doped source/drain regions are formed aligned with the disposable spacer of the transistor region and in the semiconductor substrate of a resistor region. The disposable spacer and the first insulating layer are removed. A shallowly doped source/drain region is formed aligned with the sides of the gate pattern and adjacent to the deeply doped source/drain region of the transistor region. An L-shaped spacer is formed adjacent to the sidewalls of the gate pattern of the transistor region. A suicide formation protecting layer pattern is simultaneously formed on the resistor region. A metal silicide is formed on an upper surface of the gate electrode, the deeply doped source/drain regions.

Abstract: Provided are a highly integrated semiconductor device with a silicide layer, which can secure a contact margin, and a method of manufacturing the highly integrated semiconductor device. The highly integrated semiconductor device includes a gate electrode formed on a semiconductor substrate. A source region and a drain region are formed in predetermined upper portions of the semiconductor substrate on two sides of the gate electrode such that each of the source region and the drain region includes a lightly doped drain (LDD) region and a heavily doped region. A suicide layer is formed on the gate electrode, the source region, and the drain region. The silicide layer has a sufficient thickness to function as an ohmic contact and is formed on the LDD region and the heavily doped region of each of the source region and the drain region.

Abstract: A semiconductor device includes: a silicon substrate; a source/drain region formed in the substrate including a lightly doped region and an adjacent heavily doped region, the depth of the heavily doped region being greater than the depth of the lightly doped region; a gate oxide layer on the silicon substrate; and a notched gate electrode on the substrate, the notched gate electrode including a notch along an outer side surface of a lower portion such that a top portion of the notched gate electrode is wider than the lower portion, the gate oxide layer extending between the interface of the notched gate electrode and the substrate, and a gate poly oxide layer provided along an outer side surface of the notched gate electrode and along an inner wall of the notch, a portion of the lightly doped region being under the notch.

Abstract: The present invention relates to a highly integrated SOI semiconductor device and a method for fabricating the SOI semiconductor device by reducing a distance between diodes or well resistors without any reduction in insulating characteristics. The device includes a first conductivity type semiconductor substrate and a surface silicon layer formed by inserting an insulating layer on the semiconductor substrate. A trench is formed by etching a predetermined portion of surface silicon layer, insulating layer and substrate to expose a part of the semiconductor substrate to be used for an element separating region, and a STI is formed in the trench. A transistor is constructed on the surface silicon layer surrounded by the insulating layer and STI with a gate electrode being positioned at the center thereof and with source/drain region being formed in the surface silicon layer of both edges of the gate electrode for enabling its bottom part to be in contact with the insulating layer.