Abstract: A metal/insulator/metal capacitor and a fabrication method thereof are presented. The method includes forming a first electrode on an insulation film; forming a side wall made of insulating material on a side surface of the first electrode; forming an interlayer insulation film on the top surface of the insulation film including the first electrode and the side wall; forming a via hole to expose the first electrode by selectively etching the interlayer insulation film such that an edge area at which a side surface and a bottom of the via hole intersect is positioned on a top surface of the side wall; forming a dielectric layer on an inner wall of the via hole; forming a second electrode on the dielectric layer such that the via hole is filled; and forming a metal wire on the second electrode such that the metal wire is electrically connected to the second electrode.

Abstract: A temperature sensor includes a proportional to absolute temperature (PTAT) current generator configured to generate a first current proportional to temperature, a first complementary to absolute temperature (CTAT) current generator configured to generate a second current inversely proportional to temperature, a second CTAT current generator configured to generate a third current inversely proportional to temperature, and a temperature sensing unit configured to convert the first current, the second current, and the third current into a signal related to the temperature.

Abstract: A memory device according to the present invention includes multiple refresh modes and a refresh controller. A first refresh mode can respectively select one more memory block among a plurality of banks comprising a plurality of blocks and each of all banks. In addition, the first refresh mode may perform a refresh operation with respect to selected memory blocks. The second refresh mode can select a part of the banks and perform a refresh operation of data with a selected bank. The controller may select one of the first and second refresh modes in a refresh operation.

Abstract: A semiconductor device includes a DRAM and a temperature sense circuit. The DRAM has a refresh period that varies responsive to a temperature signal. The temperature sense circuit is configured to generate the temperature signal having a first binary value in response to sensing a temperature of the DRAM of at least a first temperature level, and to generate the temperature signal having a second binary value in response to sensing a temperature of the DRAM of less than a second temperature level, wherein the second temperature value is less than the first temperature value.

Abstract: A needle alignment verification circuit includes a sensor pad, a first transmission line, a control element, a data pad, a second transmission line, and a response element. The sensor pad includes an insulation part and a conduction part. The first transmission line is electrically connected to the conduction part and to the interior of the semiconductor device. The control element asserts the first transmission line at a first logic state, and upon receiving the probe signal at the conduction part, transitions the logic state of the first transmission line to a second logic state. The second transmission line provides a predetermined signal to the data pad. The response element controls the second transmission line so that the second transmission line has the state of a verification result voltage for a misalignment state in response to the second logic state.

Abstract: Semiconductor devices having an elevated contact region and methods of fabricating the same are disclosed. A disclosed semiconductor device includes a semiconductor substrate, a gate on the semiconductor substrate, spacers on sidewalls of the gate, an epitaxial layer on the semiconductor substrate, source/drain regions within the semiconductor substrate below the epitaxial layer, and low doping concentration regions within the semiconductor below the spacers. In an example, the spacers partially overlap onto the epitaxial layer.

Abstract: Methods for forming STI structures in semiconductor devices are disclosed.

Abstract: A temperature sensor instruction signal generator, which may drive a temperature sensor, and a semiconductor memory device including the same. The temperature sensor instruction signal generator may generate an instruction signal that instruct the operation of the temperature sensor using at least one of a master clock (CLK) signal, a clock enable (CKE) signal, a row address selection (RAS) signal, a column address selection (CAS) signal, a write enable (WE) signal, and a chip selection (CS) signal, wherein the instruction signal may be enabled corresponding to at least one of a self refresh mode, an auto refresh mode, and a long tRAS mode. The semiconductor memory device may include a temperature sensor and the temperature sensor instruction signal generator.

Abstract: A temperature sensor includes a reference voltage generator, a sensing temperature controller and a first differential amplifier. The reference voltage generator generates a reference voltage having a first slope that varies in accordance with variations of a peripheral temperature, and a temperature sensing voltage having a second slope that varies in accordance with variations of the peripheral temperature. The sensing temperature controller controls an offset of an amplifier in response to a first control signal, and amplifies a voltage difference between the reference voltage and the temperature sensing voltage to generate a first differential output signal, and a second differential output signal having an inverted phase of the first differential output signal. The first differential amplifier amplifies a voltage difference between the first differential output signal and the second differential output signal to generate a sensor output signal.

Abstract: An input/output circuit for a semiconductor memory device, including a data output circuit configured to buffer output data in the semiconductor memory device in response to an input/output enable signal to output the buffered output data to an input/output signal line, a data input circuit configured to receive input data from the input/output signal line and buffer the input data to transfer the buffered input data to the semiconductor memory device, and a load controller configured to control a load on the input/output signal line in response to the input/output enable signal.

Abstract: A method of forming a trench in a semiconductor device includes forming a sacrificial layer on a silicon wafer and selectively etching the sacrificial layer to form a LOCOS opening having a predetermined width. Thermal oxidation is performed on a portion of the silicon wafer exposed through the LOCOS opening to form a LOCOS oxide layer. Also, etching is performed on the LOCOS oxide layer and the silicon wafer to a desired depth to form a trench. During this process, etching is performed such that the LOCOS oxide layer is left remaining on the silicon wafer at an area corresponding to edges of the trench. An insulation layer is deposited such that the trench is filled with a material of the insulation layer. The present invention also provides a trench in a semiconductor device used as a device isolation region formed in a silicon wafer. Upper corner areas of the silicon wafer adjacent to the trench are rounded, and a LOCOS oxide layer is formed on the corner areas.

Abstract: Semiconductor devices and methods to form a trench in a semiconductor device are disclosed. A disclosed process comprises: forming a hollow by etching a portion of a semiconductor substrate; forming a side wall layer in an inner side wall of the hollow; forming a trench by further etching the semiconductor substrate exposed through the bottom of the hollow; and filling the trench by forming an insulation film on the side wall layer and the trench.

Abstract: A method of forming a trench in a semiconductor device includes forming a sacrificial layer on a silicon wafer and selectively etching the sacrificial layer to form a LOCOS opening having a predetermined width. Thermal oxidation is performed on a portion of the silicon wafer exposed through the LOCOS opening to form a LOCOS oxide layer. Also, etching is performed on the LOCOS oxide layer and the silicon wafer to a desired depth to form a trench. During this process, etching is performed such that the LOCOS oxide layer is left remaining on the silicon wafer at an area corresponding to edges of the trench. An insulation layer is deposited such that the trench is filled with a material of the insulation layer. The present invention also provides a trench in a semiconductor device used as a device isolation region formed in a silicon wafer. Upper corner areas of the silicon wafer adjacent to the trench are rounded, and a LOCOS oxide layer is formed on the corner areas.

Abstract: A semiconductor memory device includes a core block having sub-arrays and sense amplifier regions. First and second charge storing regions are disposed at sides of the core block. First and second decoupling capacitors are formed at the first and second charge storing regions, respectively. A plurality of first voltage supply lines are disposed to supply a power supply voltage to the sense amplifier regions and are connected to one electrode of each of the first and second decoupling capacitors. A plurality of second voltage supply lines are disposed to supply a ground voltage to the sense amplifier regions and are connected to the other electrode of each of the first and second decoupling capacitors.

Abstract: Example methods of fabricating a silicon on insulator substrate are disclosed. One example method may include forming a plurality of trenches on a substrate, forming an insulation layer on the trenches, removing a portion of the insulation layer formed on the trenches to partially expose the substrate, and forming a silicon on insulator film in the substrate via the exposed portions of the substrate.

Abstract: The present invention is directed to a method of fabricating a capacitor having a metal/insulator/metal (MIM) structure, which is capable of providing a minimized semiconductor device with no capacitance variation of a capacitor. According to an aspect of the present invention, a method of fabricating a thin film capacitor comprises the steps of forming a first via and a second via which are isolated with a predetermined distance by selectively etching an interlayer insulating film formed over the entire structure of a semiconductor substrate, filling in the first via and the second via with a first metal material, forming a capacitor window by etching the interlayer insulating film between the first via and the second via to have a predetermined depth, forming a dielectric layer on an inner wall, and forming a second metal material to fill in the capacitor window.

Abstract: A semiconductor device includes a DRAM and a temperature sense circuit. The DRAM has a refresh period that varies responsive to a temperature signal. The temperature sense circuit is configured to generate the temperature signal having a first binary value in response to sensing a temperature of the DRAM of at least a first temperature level, and to generate the temperature signal having a second binary value in response to sensing a temperature of the DRAM of less than a second temperature level, wherein the second temperature value is less than the first temperature value.

Abstract: Methods for forming a gate in a semiconductor device are disclosed. In an example method, the gate is formed such that the CD of an upper portion of the gate is greater than the CD of a lower portion of the gate by performing multiple etching processes. In an illustrated example, the etching processes are performed in three stages, (i.e., a first dry etching process for etching the upper portion, a second dry etching process for etching the lower portion and a third dry etching) under three different process conditions, thereby causing a sidewall profile of the gate to have a two-layered structure.

Abstract: Semiconductor devices having an elevated contact region and methods of fabricating the same are disclosed. A disclosed semiconductor device includes a semiconductor substrate, a gate on the semiconductor substrate, spacers on sidewalls of the gate, an epitaxial layer on the semiconductor substrate, source/drain regions within the semiconductor substrate below the epitaxial layer, and low doping concentration regions within the semiconductor below the spacers. In an example, the spacers partially overlap onto the epitaxial layer.

Abstract: Semiconductor devices and methods to form a trench in a semiconductor device are disclosed. A disclosed process comprises: forming a hollow by etching a portion of a semiconductor substrate; forming a side wall layer in an inner side wall of the hollow; forming a trench by further etching the semiconductor substrate exposed through the bottom of the hollow; and filling the trench by forming an insulation film on the side wall layer and the trench.