Abstract: The present invention is directed to a method for fabricating a thin film capacitor of a metal/insulator/metal (MIM) structure, which is capable of enabling small-sizing of a semiconductor device while maintaining electrostatic capacity of a capacitor. The method comprises the steps of: forming a heterogeneous film on a lower insulation film on a structure of a semiconductor substrate; forming a plurality of projections by selectively etching the heterogeneous film; and forming a first electrode layer, a dielectric layer, and a second electrode layer on the lower insulation including the plurality of projections in order along a surface shape of the projections such that a plurality of projecting parts are formed in the first electrode layer, the dielectric layer and the second electrode layer, respectively.

Abstract: In the negative drop voltage generating apparatus of a semiconductor memory device and the method of controlling a negative voltage generation. The apparatus generates a negative voltage having a level necessary for an operating mode in the semiconductor memory device. The apparatus includes a negative drop voltage generator having first and second output terminals and a voltage separated/integrated unit connected between the first and second output terminals of the negative drop voltage generator. The voltage separated/integrated unit performs a voltage separation and connection so that the negative voltages are generated with individually different levels or with the same level through the first and second output terminals, in response to an applied control signal.

Abstract: A memory device according to the present invention includes multiple refresh modes and a refresh controller. A first refresh mode can respectively select one more memory block among a plurality of banks comprising a plurality of blocks and each of all banks. In addition, the first refresh mode may perform a refresh operation with respect to selected memory blocks. The second refresh mode can select a part of the banks and perform a refresh operation of data with a selected bank. The controller may select one of the first and second refresh modes in a refresh operation.

Abstract: A method of fabricating a semiconductor device is disclosed. An example method sequentially forms a gate insulation film and a sacrificial film on a semiconductor substrate. In addition, the example method forms a bowing hollow by selectively etching the sacrificial layer, forms gate material on the gate insulation film exposed through the bowing hollow and the sacrificial film, and forms a gate by anisotropically etching the gate material such that the gate material remains on an inner side wall of the bowing hollow.

Abstract: In the negative drop voltage generating apparatus of a semiconductor memory device and the method of controlling a negative voltage generation. The apparatus generates a negative voltage having a level necessary for an operating mode in the semiconductor memory device. The apparatus includes a negative drop voltage generator having first and second output terminals and a voltage separated/integrated unit connected between the first and second output terminals of the negative drop voltage generator. The voltage separated/integrated unit performs a voltage separation and connection so that the negative voltages are generated with individually different levels or with the same level through the first and second output terminals, in response to an applied control signal.

Abstract: A dynamic random access memory (DRAM) device, including a DRAM core having memory cells for storing data information, and a read protection unit, prevents data stored in the memory cells before power-off, from being read out at power-on.

Abstract: Example methods of fabricating a silicon on insulator substrate are disclosed. One example method may include forming a plurality of trenches on a substrate, forming an insulation layer on the trenches, removing a portion of the insulation layer formed on the trenches to partially expose the substrate, and forming a silicon on insulator film in the substrate via the exposed portions of the substrate.

Abstract: Methods for forming a gate in a semiconductor device are disclosed. In an example method, the gate is formed such that the CD of an upper portion of the gate is greater than the CD of a lower portion of the gate by performing multiple etching processes. In an illustrated example, the etching processes are performed in three stages, (i.e., a first dry etching process for etching the upper portion, a second dry etching process for etching the lower portion and a third dry etching) under three different process conditions, thereby causing a sidewall profile of the gate to have a two-layered structure.

Abstract: The present invention is directed to a thin film capacitor of a metal/insulator/metal (MIM) structure and a fabrication method thereof, which is capable of enabling small-sizing of a semiconductor device while maintaining electrostatic capacity of a capacitor. The fabrication method according to the present invention comprises the steps of: forming a plurality of grooves by selectively etching a lower insulation film on a structure of a semiconductor substrate; forming a first electrode layer, a dielectric layer and a second electrode layer in order on the lower insulation film on which the plurality of grooves are formed, such that a plurality of grooves are form in the first electrode layer, the dielectric layer and the second electrode layer, respectively, along a surface shape of the lower insulation film on which the plurality of grooves are formed; and selectively etching the second electrode layer, the dielectric layer and the first electric layer, leaving a predetermined width.

Abstract: The present invention is directed to a thin film capacitor of a metal/insulator/metal (MIM) structure and a fabrication method thereof, which is capable of preventing a leakage current caused through an edge area in the bottom of a via hole in a MIM capacitor structure.

Abstract: The present invention is directed to a method of fabricating a capacitor having a metal/insulator/metal (MIM) structure, which is capable of providing a minimized semiconductor device with no capacitance variation of a capacitor. According to an aspect of the present invention, a method of fabricating a thin film capacitor comprises the steps of forming a first via and a second via which are isolated with a predetermined distance by selectively etching an interlayer insulating film formed over the entire structure of a semiconductor substrate, filling in the first via and the second via with a first metal material, forming a capacitor window by etching the interlayer insulating film between the first via and the second via to have a predetermined depth, forming a dielectric layer on an inner wall, and forming a second metal material to fill in the capacitor window.

Abstract: The present invention is directed to a method for fabricating a thin film capacitor of a metal/insulator/metal (MIM) structure, which is capable of enabling small-sizing of a semiconductor device while maintaining electrostatic capacity of a capacitor. The method comprises the steps of: forming a heterogeneous film on a lower insulation film on a structure of a semiconductor substrate; forming a plurality of projections by selectively etching the heterogeneous film; and forming a first electrode layer, a dielectric layer, and a second electrode layer on the lower insulation including the plurality of projections in order along a surface shape of the projections such that a plurality of projecting parts are formed in the first electrode layer, the dielectric layer and the second electrode layer, respectively.

Abstract: A semiconductor memory device includes a core block having sub-arrays and sense amplifier regions. First and second charge storing regions are disposed at sides of the core block. First and second decoupling capacitors are formed at the first and second charge storing regions, respectively. A plurality of first voltage supply lines are disposed to supply a power supply voltage to the sense amplifier regions and are connected to one electrode of each of the first and second decoupling capacitors. A plurality of second voltage supply lines are disposed to supply a ground voltage to the sense amplifier regions and are connected to the other electrode of each of the first and second decoupling capacitors.

Abstract: A method of fabricating a semiconductor device is disclosed. An example method sequentially forms a gate insulation film and a sacrificial film on a semiconductor substrate. In addition, the example method forms a bowing hollow by selectively etching the sacrificial layer, forms gate material on the gate insulation film exposed through the bowing hollow and the sacrificial film, and forms a gate by anisotropically etching the gate material such that the gate material remains on an inner side wall of the bowing hollow.

Abstract: Semiconductor devices and methods to form a trench in a semiconductor device are disclosed. A disclosed process comprises: forming a hollow by etching a portion of a semiconductor substrate; forming a side wall layer in an inner side wall of the hollow; forming a trench by further etching the semiconductor substrate exposed through the bottom of the hollow; and filling the trench by forming an insulation film on the side wall layer and the trench.

Abstract: A method of formation a gate in a semiconductor device includes forming a gate oxide layer and a sacrificial layer on a semiconductor substrate. The sacrificial layer is then selectively etched to form a sidewall opening. Next, a polycrystalline silicon layer is formed on an area of the gate oxide layer exposed through the sidewall opening and on the sacrificial layer. Anisotropic etching of the polycrystalline silicon layer is performed such that sidewall gates are formed by remaining portions of the polycrystalline silicon layer on sidewalls of the sidewall opening, a width of the sidewall gates corresponding to a desired width of a gate. The sacrificial layer is removed following etching of the polycrystalline silicon layer.

Abstract: A method of forming a trench in a semiconductor device includes forming a polish stop layer on a semiconductor substrate. The polish stop layer and the semiconductor substrate are then etched to form a trench. The semiconductor substrate is etched to a predetermined depth. Also, etching is performed such that ends of the polish stop layer adjacent to the trench are rounded. Next, an insulation layer that fills the trench is formed.

Abstract: A method of forming a trench in a semiconductor device includes forming a sacrificial layer on a silicon wafer and selectively etching the sacrificial layer to form a LOCOS opening having a predetermined width. Thermal oxidation is performed on a portion of the silicon wafer exposed through the LOCOS opening to form a LOCOS oxide layer. Also, etching is performed on the LOCOS oxide layer and the silicon wafer to a desired depth to form a trench. During this process, etching is performed such that the LOCOS oxide layer is left remaining on the silicon wafer at an area corresponding to edges of the trench. An insulation layer is deposited such that the trench is filled with a material of the insulation layer. The present invention also provides a trench in a semiconductor device used as a device isolation region formed in a silicon wafer. Upper corner areas of the silicon wafer adjacent to the trench are rounded, and a LOCOS oxide layer is formed on the corner areas.

Abstract: In fabricating a shallow trench isolation (STI), a silicon oxide layer, a silicon nitride layer and a moat pattern is sequentially deposited on a silicon substrate. Next, the silicon nitride layer and the silicon oxide layer is etched using the moat pattern as a mask to thereby partially expose the silicon substrate and then the moat pattern is removed. Ion implanting process is performed into the silicon substrate using the silicon nitride layer as a mask, adjusting a dose of an implanted ion and an implant energy, to thereby form an isolation region. And then, the isolation region to form a porous silicon and to form an air gap in the porous silicon is anodized, wherein a porosity of the porous silicon is determined by the dose of the implanted ion. Next, the porous silicon is oxidized through an oxidation process. Finally, the silicon nitride layer is removed.

Abstract: In fabricating a shallow trench isolation (STI), a silicon oxide layer, a silicon nitride layer and a moat pattern is sequentially deposited on a silicon substrate. Next, the silicon nitride layer and the silicon oxide layer is etched using the moat pattern as a mask to thereby partially expose the silicon substrate and then the moat pattern is removed. Ion implanting process is performed into the silicon substrate using the silicon nitride layer as a mask, adjusting a dose of an implanted ion and an implant energy, to thereby form an isolation region. And then, the isolation region to form a porous silicon and to form an air gap in the porous silicon is anodized, wherein a porosity of the porous silicon is determined by the dose of the implanted ion. Next, the porous silicon is oxidized through an oxidation process. Finally, the silicon nitride layer is removed.