Patents by Inventor Young Hwan Son

Young Hwan Son has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11963358
    Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.
    Type: Grant
    Filed: February 1, 2023
    Date of Patent: April 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyo Joon Ryu, Young Hwan Son, Seo-Goo Kang, Jung Hoon Jun, Kohji Kanamori, Jee Hoon Han
  • Patent number: 11948745
    Abstract: A multilayer capacitor includes: a body including a capacitance region in which at least one first internal electrode and at least one second internal electrode are alternately stacked on each other interposing at least one dielectric layer therebetween in a first direction; and first and second external electrodes disposed on the body and spaced apart from each other to be respectively connected to the at least one first internal electrode and the at least one second internal electrode, wherein the body includes a side margin overlapping none of the at least one first internal electrode and the at least one second internal electrode in the first direction, and a center width of the side margin is greater than a minimum width of the side margin.
    Type: Grant
    Filed: April 20, 2022
    Date of Patent: April 2, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Won Chul Sim, Soo Hwan Son, Young Ghyu Ahn
  • Patent number: 11916244
    Abstract: A battery module includes a module housing including a first plate in which one side is open, a second plate coupled with the first plate to form an internal space, and a partition member disposed across the internal space to couple the first plate with the second plate; and a battery cell stack disposed in the internal space, in which a plurality of battery cells are stacked.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: February 27, 2024
    Assignee: SK On Co., Ltd.
    Inventors: Seok Hwan Lee, Hae Ryong Jeon, Seung Hoon Ju, Young Sun Choi, Myeong Hwan Ma, Sol San Son
  • Patent number: 11864384
    Abstract: A nonvolatile memory device includes a mold structure having a stack of word lines on a substrate and first and second string selection lines on the word lines, a first cutting structure through the mold structure, a second cutting structure through the mold structure, the second cutting structure being spaced apart from the first cutting structure, a channel structure penetrating the mold structure to be connected to the substrate, the channel structure being between the first and second cutting structures, a first cutting line cutting through the first string selection line but not through the second string selection line, the first cutting line being between the first and second cutting structures, and a second cutting line cutting through the second string selection line but not through the first string selection line, the second cutting line being between the second cutting structure and the channel structure.
    Type: Grant
    Filed: January 20, 2022
    Date of Patent: January 2, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je Suk Moon, Seo-Goo Kang, Young Hwan Son, Kohji Kanamori, Jee Hoon Han
  • Publication number: 20230292515
    Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.
    Type: Application
    Filed: May 22, 2023
    Publication date: September 14, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Young-Hwan SON, Kohji KANAMORI, Shin-Hwan KANG, Young Jin KWON
  • Publication number: 20230248865
    Abstract: A sterilizer is provided to include: a first pipe having an inner wall with a light reflecting property; a second pipe disposed in the first pipe so as to pass fluid therethrough and formed of a light transmitting material; and a plurality of UV LEDs arranged on the inner wall of the first pipe and configured to irradiate sterilization UV light onto the fluid.
    Type: Application
    Filed: April 17, 2023
    Publication date: August 10, 2023
    Inventors: Seong Min LEE, Young Hwan SON, Jae Seon YI, Jong Rack KIM, Ik Hwan KO
  • Patent number: 11696442
    Abstract: A vertical memory device includes gate electrodes on a substrate, a channel extending through the gate electrodes, and a contact plug extending through the gate electrodes. The gate electrodes are stacked in a first direction substantially vertical to an upper surface of the substrate and arranged to have a staircase shape including steps of which extension lengths in a second direction substantially parallel to the upper surface gradually increase from a lowermost level toward an uppermost level. A pad at an end portion of each of the gate electrodes in the second direction has a thickness greater than those of other portions thereof. The channel extends in the first direction. The contact plug extends in the first direction. The channel contacts the pad of a first gate electrode among the gate electrodes to be electrically connected thereto, and is electrically insulated from second gate electrodes among the gate electrodes.
    Type: Grant
    Filed: August 12, 2020
    Date of Patent: July 4, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hwan Son, Kohji Kanamori, Shin-Hwan Kang, Young Jin Kwon
  • Publication number: 20230189525
    Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.
    Type: Application
    Filed: February 1, 2023
    Publication date: June 15, 2023
    Inventors: Hyo Joon RYU, Young Hwan SON, Seo-Goo KANG, Jung Hoon JUN, Kohji KANAMORI, Jee Hoon HAN
  • Patent number: 11628232
    Abstract: A sterilizer may include: a first pipe having an inner wall with a light reflecting property; a second pipe disposed in the first pipe so as to pass fluid therethrough and formed of a light transmitting material; and a plurality of UV LEDs arranged on the inner wall of the first pipe and configured to irradiate sterilization UV light onto the fluid.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: April 18, 2023
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Seong Min Lee, Young Hwan Son, Jae Seon Yi, Jong Rack Kim, Ik Hwan Ko
  • Patent number: 11581331
    Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: February 14, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyo Joon Ryu, Young Hwan Son, Seo-Goo Kang, Jung Hoon Jun, Kohji Kanamori, Jee Hoon Han
  • Publication number: 20220139957
    Abstract: A nonvolatile memory device includes a mold structure having a stack of word lines on a substrate and first and second string selection lines on the word lines, a first cutting structure through the mold structure, a second cutting structure through the mold structure, the second cutting structure being spaced apart from the first cutting structure, a channel structure penetrating the mold structure to be connected to the substrate, the channel structure being between the first and second cutting structures, a first cutting line cutting through the first string selection line but not through the second string selection line, the first cutting line being between the first and second cutting structures, and a second cutting line cutting through the second string selection line but not through the first string selection line, the second cutting line being between the second cutting structure and the channel structure.
    Type: Application
    Filed: January 20, 2022
    Publication date: May 5, 2022
    Inventors: Je Suk MOON, Seo-Goo KANG, Young Hwan SON, Kohji KANAMORI, Jee Hoon HAN
  • Patent number: 11296110
    Abstract: A nonvolatile memory device includes a mold structure including a plurality of insulating patterns and a plurality of gate electrodes alternately stacked on a substrate, a semiconductor pattern penetrating through the mold structure and contacting the substrate, a first charge storage film, and a second charge storage film separated from the first charge storage film. The first and second charge storage films are disposed between each of the gate electrodes and the semiconductor pattern. Each of the gate electrodes includes a first recess and a second recess which are respectively recessed inward from a side surface of the gate electrodes. The first charge storage film fills at least a portion of the first recess, and the second charge storage film fills at least a portion of the second recess.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwang Young Jung, Jong Won Kim, Young Hwan Son, Jee Hoon Han
  • Patent number: 11233065
    Abstract: A nonvolatile memory device includes a mold structure having a stack of word lines on a substrate and first and second string selection lines on the word lines, a first cutting structure through the mold structure, a second cutting structure through the mold structure, the second cutting structure being spaced apart from the first cutting structure, a channel structure penetrating the mold structure to be connected to the substrate, the channel structure being between the first and second cutting structures, a first cutting line cutting through the first string selection line but not through the second string selection line, the first cutting line being between the first and second cutting structures, and a second cutting line cutting through the second string selection line but not through the first string selection line, the second cutting line being between the second cutting structure and the channel structure.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: January 25, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Je Suk Moon, Seo-Goo Kang, Young Hwan Son, Kohji Kanamori, Jee Hoon Han
  • Publication number: 20210361802
    Abstract: A sterilizer may include: a first pipe having an inner wall with a light reflecting property; a second pipe disposed in the first pipe so as to pass fluid therethrough and formed of a light transmitting material; and a plurality of UV LEDs arranged on the inner wall of the first pipe and configured to irradiate sterilization UV light onto the fluid.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Inventors: Seong Min LEE, Young Hwan SON, Jae Seon YI, Jong Rack KIM, Ik Hwan KO
  • Publication number: 20210313344
    Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.
    Type: Application
    Filed: November 23, 2020
    Publication date: October 7, 2021
    Inventors: Hyo Joon RYU, Young Hwan SON, Seo-Goo KANG, Jung Hoon JUN, Kohji KANAMORI, Jee Hoon HAN
  • Patent number: 11083809
    Abstract: A sterilizer may include: a first pipe having an inner wall with a light reflecting property; a second pipe disposed in the first pipe so as to pass fluid therethrough and formed of a light transmitting material; and a plurality of UV LEDs arranged on the inner wall of the first pipe and configured to irradiate sterilization UV light onto the fluid.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: August 10, 2021
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Seong Min Lee, Young Hwan Son, Jae Seon Yi, Jong Rack Kim, Ik Hwan Ko
  • Patent number: 11031411
    Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 8, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hwan Son, Jae-Hoon Jang, Jee-Hoon Han
  • Patent number: 10978464
    Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.
    Type: Grant
    Filed: May 14, 2020
    Date of Patent: April 13, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Hwan Son, Jae-Hoon Jang, Jee-Hoon Han
  • Patent number: 10928083
    Abstract: An air conditioner including a body having an evaporator for heat-exchanging air flowing in the body, and an air purifying module coupled to the body. The air purifying module may have a light emitting diode part disposed along a flow path of the air to provide ultraviolet rays, and a filter part disposed adjacent to the light emitting diode part.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: February 23, 2021
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jung Yeol Park, Young Hwan Son, Seong Min Lee, Jae Seon Yi, Jong Hyun Koo, Sang Hee Cho, Ju Won Yoo, Sung Lim Cho, Jong Rack Kim
  • Patent number: 10886289
    Abstract: In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: January 5, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shin-hwan Kang, Young-hwan Son, Dong-seog Eun, Chang-sup Lee, Jae-hoon Jang