Abstract: The present invention relates to a negative electrode including a negative electrode current collector, and a negative electrode active material layer disposed on the negative electrode current collector, wherein the negative electrode active material layer includes a negative electrode active material containing a silicon-based active material and a carbon-based active material at a weight ratio of 12:88 to 28:72, and a ratio of D50 of the carbon-based active material to D90 of the silicon-based active material is 2 to 5.

Abstract: Provided is a storage device capable of increasing its life cycle and operating method thereof. The storage device includes a nonvolatile memory device that stores data and a controller that controls the nonvolatile memory device. The controller receive can modify a write time-out value of the nonvolatile memory device in accordance with predetermined conditions, such as request from a host or exceeding of a predefined life cycle.

Abstract: A semiconductor package is disclosed. The semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias.

Abstract: A power supply device includes; first/second boost circuits that boost voltages applied to a first/second boost nodes in response to a first/second main signals, and respectively operated first/second transmission unit that control provision of boosted voltages to an output node. The power supply device also includes a bulk voltage controller connected between the boosted nodes and controlling a connection between the output node and a bulk node in response to a bulk control signal. Voltages respectively applied to the first and second transmission units are determined in response to an output node voltage, as well as the first/second main signals.

Abstract: A memory device comprising: at least one bank of memory cells that receives a first clock for clocking commands and a second clock for clocking data, wherein the second clock is activated based on a first command and deactivated based on a second command. The memory device further including a clock activation circuit configured to generate an enable signal based on the first command and a disable signal based on the second command, and a clock generator configured to generate the second clock based on a reference clock upon receipt of the enable signal.

Abstract: A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.

Abstract: A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.

Abstract: Provided is a storage device capable of increasing its life cycle and operating method thereof. The storage device includes a nonvolatile memory device that stores data and a controller that controls the nonvolatile memory device. The controller receive can modify a write time-out value of the nonvolatile memory device in accordance with predetermined conditions, such as request from a host or exceeding of a predefined life cycle.

Abstract: A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.

Abstract: A power supply device includes; first/second boost circuits that boost voltages applied to a first/second boost nodes in response to a first/second main signals, and respectively operated first/second transmission unit that control provision of boosted voltages to an output node. The power supply device also includes a bulk voltage controller connected between the boosted nodes and controlling a connection between the output node and a bulk node in response to a bulk control signal. Voltages respectively applied to the first and second transmission units are determined in response to an output node voltage, as well as the first/second main signals.

Abstract: A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first voltage, and disables the sub-word line of a non-selected memory cell to a second voltage and a third voltage, in response to a sub-word line enable signal, a first word line driving signal, and a second word line driving signal. The delay logic circuit controls the semiconductor memory device so that an amount of charge of the sub-word line that is introduced to the third voltage is greater than an amount of charge of the sub-word line that is introduced to the second voltage by changing a transition point of time of the sub-word line enable signal with respect to a transition point of time of the first word line driving signal, during the disabling of the sub-word line.

Abstract: A semiconductor memory device including a bit line connected to a memory cell and a sense amplifier configured to drive a voltage level of a global bit line in response to a voltage level of the bit line. The sense amplifier provides data that is complementary to data stored in the memory cell to the global bit line and provides the complementary data of the global bit line to the memory cell during an active operation of the memory cell.

Abstract: A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.

Abstract: A semiconductor package is disclosed. The semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias.

Abstract: A CMOS charge pump with improved latch-up immunity is provided. The CMOS charge pump includes a blocking transistor that disconnects first and second boost nodes from a bulk node in response to a blocking control signal, such that a bulk voltage can be maintained at a predetermined level or higher. The CMOS charge pump in a power-up period first precharges the bulk voltage before the main pump performs a boosting operation and prevents a latch-up phenomenon.

Abstract: A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.

Abstract: An input/output circuit includes an I/O node connected to a pull up and pull down circuit having a pull up and pull down transistors. Data is sent and received at through the I/O node. A level shifter provides voltages including a supply voltage and a high voltage higher than the supply voltage. A signal control circuit controls the voltage level applied to the pull up and pull down circuit. During a data input mode, data is received at the I/O node and the pull up transistor is biased at the high voltage to cut off the pull up transistor. During a data output mode, data is output at the I/O node and the pull down transistor pulls down the I/O node to ground when the output data is low, and the pull up transistor is activated when the output data is high.

Abstract: An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.

Abstract: A semiconductor memory device for reducing ripple noise of a back-bias voltage, and a method of driving the semiconductor memory device include a word line driving circuit and a delay logic circuit. The word line driving circuit enables a sub-word line connected to a selected memory cell to a first voltage, and disables the sub-word line of a non-selected memory cell to a second voltage and a third voltage, in response to a sub-word line enable signal, a first word line driving signal, and a second word line driving signal. The delay logic circuit controls the semiconductor memory device so that an amount of charge of the sub-word line that is introduced to the third voltage is greater than an amount of charge of the sub-word line that is introduced to the second voltage by changing a transition point of time of the sub-word line enable signal with respect to a transition point of time of the first word line driving signal, during the disabling of the sub-word line.

Abstract: A memory device comprising: at least one bank of memory cells that receives a first clock for clocking commands and a second clock for clocking data, wherein the second clock is activated based on a first command and deactivated based on a second command. The memory device further including a clock activation circuit configured to generate an enable signal based on the first command and a disable signal based on the second command, and a clock generator configured to generate the second clock based on a reference clock upon receipt of the enable signal.