SEMICONDUCTOR MEMORY DEVICE
A semiconductor package is disclosed. The semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias.
This application claims the benefit of Korean Patent Application No. 10-2010-0086580, filed on Sep. 3, 2010 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
BACKGROUNDOne or more aspects of the disclosed embodiments relate to semiconductor memory devices, and more particularly, to a semiconductor memory device for efficiently controlling a stacked structure of semiconductor memory chips.
As high integration degree and high performance of semiconductor memory devices have been continuously required, importance of a stacked structure of semiconductor memory chips has increased. In addition, due to the compact stacked structure of such semiconductor memory devices, unwanted interference and heat associated with accessing the device occurs more frequently. Accordingly, there is a need to efficiently control a stacked structure of semiconductor memory chips, to maintain the highly integrated configuration of the semiconductor memory chips, and to reduce interference and excessive heat associated with stacked semiconductor memory chips.
SUMMARYOne or more aspects of the disclosed embodiments provide semiconductor memory devices, including semiconductor packages, for efficiently controlling a stacked structure of semiconductor memory chips.
In one embodiment, a semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential signal providing first information, and includes an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias.
In another embodiment, a semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential input signal providing first information, and includes an output to provide a differential output signal including the first information in a differential signal format to at least one of the plurality of stacks of through substrate vias.
In another embodiment, a semiconductor package includes a package interface, a stack of semiconductor chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip. The interface circuit includes an input connected to the first pair of terminals to receive a differential input signal providing first information, and includes an output to provide an output signal including the first information to at least one of the plurality of stacks of through substrate vias. The interface circuit is configured to interpret the differential input signal as a multi-level signal, and to provide the output signal based on the interpreted multi-level signal.
In another embodiment, a semiconductor package includes package terminals connectable to an address bus, a stack of memory chips, an interface circuit, and a plurality of stacks of through substrate vias. The interface circuit includes an address buffer connected to the package terminals to receive an external address, an address translation circuit connected to receive the external address from the address buffer, and having an output of an internal address, and a monitoring circuit configured to monitor an amount of access operations to at least one memory location of the stack of memory chips and provide a corresponding monitoring result. Each stack of through substrate vias include plural through substrate vias of respective ones of the memory chips of the stack, each through substrate via electrically connected to a through substrate via of a immediately adjacent memory chip, each stack of through substrate vias connected to receive the internal address at the output of the address translation circuit. The address translation circuit is configured to translate the external address to an internal address in response to at least the monitoring result of the monitoring circuit.
In another embodiment, a semiconductor package includes package terminals, a stack, of memory chips, an interface circuit, and a plurality of stacks of through substrate vias. The interface circuit includes an address buffer connected to the package terminals to receive an external address, and an address translation circuit connected to receive the external address from the address buffer, and having an output that outputs an internal address. Each stack of through substrate vias include plural through substrate vias of respective ones of the memory chips each electrically connected to a through substrate via of an immediately adjacent memory chip, each stack of the plurality of stacks of through substrate vias connected to receive an internal address at the output of the address translation circuit. The interface circuit further includes a refresh controller in logical communication with the package terminals and configured to receive an external refresh control signal, the refresh controller operable to output a series of internal refresh control signals, each of the series of internal refresh control signals operable to initiate a memory refresh of different parts of the stack of memory chips.
In another embodiment, a semiconductor package includes a package interface, a stack of memory chips, a plurality of stacks of through substrate vias, and an interface circuit. The package interface includes package terminals including at least a first pair of terminals. Each stack of through substrate vias includes plural through substrate vias of respective ones of the memory chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent memory chip. The interface circuit includes: an input connected to the first pair of terminals to receive a differential signal providing first information, and including an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias; an address buffer connected to a plurality of the package terminals to receive an external address; an address translation circuit connected to receive the external address from the address buffer, and having an output of an internal address; a monitoring circuit configured to monitor an amount of access operations to at least one memory location of the stack of memory chips and provide a corresponding monitoring result; and a refresh controller in logical communication with a plurality of the package terminals and configured to receive an external refresh control signal, the refresh controller operable to output a series of internal refresh control signals, each of the series of internal refresh control signals operable to initiate a memory refresh of different parts of the stack of memory chips. The address translation circuit is configured to translate the external address to an internal address in response to at least the monitoring result of the monitoring circuit.
In another embodiment, a method of refreshing a stack of memory chips in a semiconductor package is disclosed. The method includes receiving a single external refresh command, and in response to the single external refresh command, refreshing first and second chips of the stack of memory chips in sequential order.
Exemplary embodiments discussed herein will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which:
Hereinafter, exemplary embodiments will be described in detail with reference to the accompanying drawings. Like reference numerals denote like elements throughout the drawings. The disclosed embodiments may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein.
It will be understood that when an element or layer is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected, coupled, or adjacent to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” “directly adjacent to,” another element or layer, or the like, there are no intervening elements or layers present. Like numerals refer to like elements throughout. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Embodiments are described herein with reference to cross-sectional or perspective illustrations that are schematic illustrations of idealized embodiments (and intermediate structures). As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, embodiments should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an edge or corner region illustrated as having sharp edges may have somewhat rounded or curved features. Likewise, elements illustrated as circular or spherical may be oval in shape or may have certain straight or flattened portions. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region or element of a device and are not intended to limit the scope of the disclosed embodiments.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In one embodiment, each of the semiconductor memory chips MCs includes a storage region ARY for storing data DTA. Although
In
In some instances, respective through substrate vias pass entirely through each respective chip in a stack of chips. However, in other instances, one or more through substrate vias passing through one or more respective chips only pass partly through the chip, and then connect to circuitry within the chip. The circuitry is electrically connected to the through substrate via, and may electrically connect to a pad or other electrically conductive element that connects to a through substrate via of a next, immediately adjacent chip. Also, certain through substrate vias may pass through certain chips without electrically connecting to circuitry in the chip.
In one embodiment, the stacked chips align vertically, and each chip has the same planar dimensions. As such, outer edges of the chips may align as well. In addition, the chips may have the same thickness, and may be identical chips. However, the stack of chips need not include all chips having the same dimensions, and some chips in the stack of chips can have smaller dimensions than others, or can be shifted in a lateral direction compared to others so that the outer edges of the chips do not align.
The external I/O unit EIO may be a system data bus connected to an external memory controller MCT. The signal SIG transmitted via the internal I/O unit IIO or the external I/O unit EIO may be an address signal including an address Addr, data signal including data DTA, and/or a command signal including a command CMD for operating the semiconductor memory device MD.
In one embodiment, the interface control circuit ICC that performs as an interface among the stacked structure of the semiconductor memory chips MCs, the internal I/O unit IIO, and the external I/O unit EIO is included in the semiconductor memory device MD and may be in various forms, as will be described below.
As described above, the internal I/O unit IIO may be through electrodes (e.g., through-substrate vias, or more specifically through-silicon vias), labeled “TSV,” for electrically connecting the interface control circuit ICC to the slave memory chips SLAs. The through electrodes TSV of the internal I/O unit IIO may be disposed for receiving the address Addr, the data DTA, or the command CMD, respectively. In one embodiment, since the interface control circuit ICC is included in the master memory chip MAS, the internal I/O unit IIO that connects the interface control circuit ICC to the master memory chip MAS may be formed of an internal electric wire (not shown). Referring to
For example, referring to
The semiconductor memory device MD may include the through electrodes TSV each arranged as a stack of through substrate vias, each through substrate via of the stack passing through a respective chip. For example, as shown in
Although not shown in
In
For high-bandwidth transmission, the semiconductor memory device MD according to one embodiment may provide an interface optimized for a stacked structure of the semiconductor memory chips. To this end, in the semiconductor memory device MD, an I/O type employed by the internal I/O unit IIO an I/O type employed by the external I/O unit EIO may be combined in various ways, as will be described below in detail.
Referring to
The first I/O type may be one of various I/O types introduced in the table of
If the first I/O type is the single-ended I/O type and the second I/O type is the differential I/O type, the semiconductor memory device MD requires 6400 through electrodes that operate at a data (transmission) rate of 200 Mbps (Case 1). That is, if the first I/O type is the single-ended I/O type, a product of the number of through electrodes required and a data rate of each of the through electrodes should satisfy a bandwidth required by the semiconductor memory device MD.
In this case, the number of through electrodes required varies according to the data rates of the through electrodes at even the same bandwidth. For example, when the data rates of the through electrodes of the semiconductor memory device MD double, e.g., 400 Mbps, 3200 through electrodes are required for the semiconductor memory device MD to have a bandwidth of 160 GB/sec (Case 2). The data rate of each of the through electrodes may be adjusted by changing a burst length of data (signal) transmitted/received via each of the through electrodes. In other words, a comparison of Case 1 and Case 2 reveals that the data rate of the through electrode also doubles when the burst length of data doubles.
Thus, if the burst length of data is set to ‘4’, the semiconductor memory device MD requires 1600 through electrodes that operate at a data rate of 800 Mbps under the same conditions (Case 3).
Accordingly, if the first I/O type is the single-ended I/O type and the second I/O type is the differential I/O type, the I/O interface unit IU of
Referring to
The I/O interface unit IU may further include a receiver TSVR that receives an internal signal SIG3 via the internal I/O unit IIO according to the single-ended I/O type, and a serializer SER that converts the internal signal SIG3 received from the receiver TSVR into a serial signal SIG4 and transmits the serial signal SIG4 via the external I/O unit EIO.
Referring back to
However, if in the multi-level I/O type, the burst length of data is set to ‘2’, the semiconductor memory device MD requires 1600 through electrodes that operate at a data rate of 800 Mbps under the same conditions (Case 5). If the burst length of data is set to ‘4’, the semiconductor memory device MD also requires 1600 through electrodes that operate at a data rate of 800 Mbps under the same conditions (Case 6).
Lastly, when the internal I/O unit IIO is driven according to the differential I/O type, the semiconductor memory device MD requires 12800 through electrodes that operate at a data rate of 200 Mbps (Case 7). That is, if the first I/O type is the differential I/O type, a product of twice as many as the number of through electrodes required and the data rate of each of the through electrodes should satisfy a bandwidth required by the semiconductor memory device MD.
However, if the burst length of data is set to ‘2’ when the internal I/O unit IIO is driven according to the differential I/O type, the semiconductor memory device MD requires 6400 through electrodes that operate at a data rate of 400 Mbps (Case 8). Similarly, if the burst length of data is set to ‘4’, the semiconductor memory device MD requires 3200 through electrodes that operate at a data rate of 800 Mbps under the same conditions (Case 9).
Various combinations of I/O types employed by an internal I/O unit and an external I/O unit of a semiconductor memory device according to various embodiments, respectively, have been described above. As described above, the semiconductor memory device may determine I/O types to be employed by the internal I/O unit and the external I/O unit, respectively, based on a number of through electrodes required. Also, the semiconductor memory device may determine I/O types to be employed by the internal I/O unit and the external I/O unit, based on a data rate of each of the through electrodes. However, the inventive concept is not limited to the above description. In addition, in one embodiment, an interface control circuit may be configured such that only certain signal types, such as data signals, are converted between different I/O types (e.g., from differential to single-ended), while other signal types, such as address or control signals or power connections, are not converted between different I/O types. That is, in one embodiment, only data signals are converted between different I/O types by an interface control circuit ICC.
An I/O interface unit IU of the semiconductor memory device may perform interfacing for various I/O protocols so as to provide an interface optimized for a stacked structure of semiconductor memory chips that operate at a high bandwidth.
Referring back to
An interface control circuit ICC included in the master memory chip MAS may exchange a signal with corresponding slave memory chips SLAs via the through electrodes TSV of
Referring to
The second master memory chip MAS2 may be disposed on the third slave memory chip SLA3 furthest from the first master memory chip MAS1 from among the slave memory chips SLA1 to SLA3, in which input and output of data are controlled by the first interface control circuit ICC1. The second master memory chip MAS2 may be connected to the first master memory chip MAS1 on a substrate SUB (e.g., a package substrate, not shown in
Referring to
When one semiconductor memory device includes a plurality of master memory chips, different identifiers may be assigned to the master memory chips, respectively, so that only a master memory chip assigned a desired identifier may operate at a certain time, thereby preventing the master memory chips from being activated simultaneously. Such controlling may be performed by the memory controller MCT of
A case where an interface control circuit ICC as illustrated in
For example, referring to
A number of semiconductor memory chips to be included in the semiconductor memory device MD of
Referring to
Referring back to
To this end, referring to
The interface control circuits illustrated in
An interface control circuit of a semiconductor memory device according to one embodiment may have a structure and a function for preventing the performance of a semiconductor memory chip from being degraded, caused by being excessively accessed from among a stacked structure of semiconductor memory chips or for preventing a coupling phenomenon or an error from occurring between the stacked structure of semiconductor memory chips, as will be described in detail below.
If a semiconductor memory device MD includes a stacked structure of semiconductor memory chips MCs as illustrated in
In one embodiment, it may be assumed that the stacked structure of semiconductor memory chips MCs have a storage region having the same size and structure. That is, if a chip address is changed, the same storage region of another memory chip corresponding to an address to be accessed may be accessed.
The address scrambler AS may scramble the chip addresses MCaddrs having different values assigned to the plurality of semiconductor memory chips and output changed chip addresses MCaddrs′, in response to a control signal XCON. In one embodiment, a controller may track the free memory space in different chips, and if the controller determines that one region of a first chip (e.g., a bank, block, or wordline) is being overused and a same region of a second chip is available (i.e., has no data stored in it), the controller can scramble the chip addresses MCaddrs into changed chip addresses MCaddrs′ and the data in the region of the first chip can be written to the same region on the second chip so that during subsequent accesses, the second chip is accessed rather than the first chip, reducing the usage of the overused region of the first chip. Although address changes above are described in terms of changing chip addresses, other addresses, such as memory bank addresses among different chips or within the same chip, can be changed as well.
In another embodiment, instead of tracking free memory space, when a region of a first chip is determined to be overused, even if a same region of a second chip has data stored in it, a third region of one of the chips or a third chip can be used as a temporary storage (i.e., a buffer), so that data stored in the second chip could be stored in the buffer, and then data from the first chip can be moved to the second chip, data in the buffer can be moved to the first chip, and then the chip addresses MCaddrs can be scrambled to output changed chip addresses MCaddrs′ so those two memory regions are swapped when subsequently accessing memory.
Although not illustrated in
The address scrambler AS according to one exemplary embodiment may scramble a chip address in one of various forms as will be described above with reference to
Referring to
That is, in one embodiment, the address scrambler AS may scramble between an even-numbered chip address and an odd-numbered chip address, in response to a control signal XCON, but is not limited thereto.
In the embodiment described above, scrambling of an address scrambler is performed according to a control signal XCON. In one embodiment, the control signal XCON for controlling an address scrambler AS may be generated using a counter CT included in an interface control circuit ICC, as illustrated in
Referring to
Otherwise, referring to
The counting described above in connection with
In one embodiment, the control signal XCON may include information regarding a scrambling method, together with information indicating whether scrambling is to be performed. For example, the control signal XCON may indicate whether the scrambling method illustrated in
In one embodiment, the counters CT illustrated in
Referring back to
Referring to
Both the address scramblers AS included in the interface chip IC of
As described above, a semiconductor memory device according to an exemplary embodiment may prevent an error from occurring therein, caused when a semiconductor memory chip is accessed excessively from among a stacked structure of semiconductor memory chips, by scrambling chip addresses of the semiconductor memory chips. Furthermore, the semiconductor memory device may prevent a bank from being accessed excessively from among banks of a stacked structure of semiconductor memory chips by scrambling bank addresses of the banks, as will be described below with reference to
For example, the address scrambler AS may perform an operation as illustrated in
When an address scrambler according to one embodiment performs scrambling on the chip address MCaddr and/or the bank address BAaddr as illustrated in
An address scrambler according to another exemplary embodiment may scramble an address of a first storage region A and output an address of another storage region B from among storage regions of a stacked structure of semiconductor memory chips, as illustrated in
As described above, an address scrambler according to certain embodiments may prevent a particular semiconductor memory chip, bank or storage region from being accessed excessively from among a stacked structure of semiconductor memory chips, banks or storage regions by scrambling a received address. However, the address translation described herein may also be used in systems that do not include a stack of chips or that do not include through substrate vias. For example, the address translation described above may be used in a semiconductor device that includes a stack of chips connected through wire bonding, or through a plurality of chips disposed on a board or substrate but not in a stacked configuration. In addition, the address translation may occur within a single chip, between different memory banks or different memory regions within the single chip. Nonetheless, the translation method is particularly useful in stacked chip packages to avoid the over-use of a particular chip or particular bank or region from rendering the entire package defective or inoperable.
Referring to
Exemplary refresh controllers according to various embodiments will now be described in greater detail with reference to the accompanying drawings.
Referring to
In this case, the refresh signal XRefr is transmitted to a command through electrode CMT passing through a stack of chips and that transmits a command, and the chip selection signal CSEL is transmitted to a chip selection through electrode CST passing through the stack of chips and that transmits chip address MCaddrs, via a selector MUX. In an embodiment where the interface control circuit ICC is included in the master memory chip MAS as illustrated in
In one embodiment, the selector MUX is included in the interface control circuit ICC. If refreshing is performed, then the selector MUX receives the chip selection signal CSEL from the refresh controller RC and transmits it to the chip selection through electrode CST. Then a semiconductor memory device corresponding to the chip selection signal CSEL is activated from among semiconductor memory chips MAS, SLA1, SAL2, and SLA3 that receive the chip selection signal CSEL via the chip selection through electrode CST. If refreshing is not performed, the selector MUX transmits the chip address MCaddr to the chip selection through electrode CST.
Although not shown in
If the refresh command CMD_Refr is input to the refresh controller RC of
Each of the chip selection signals CSEL may be a 2-bit signal. If the four semiconductor memory chips MAS, SLA1, SLA2, and SLA3 are assigned chip identifiers (chip addresses), e.g., ‘00’, ‘01’, ‘10’, and ‘11’, respectively, as illustrated for example in
In another embodiment, if the refresh command CMD_Refr is input to the refresh controller RC of
Referring to
Referring to exemplary
As depicted in
The sequence for refreshing semiconductor memory chips may include different patterns. For example, as explained above, the sequence may depend on a chip ID assigned to the different chips. In other cases, chips may be associated with a mode register set (MRS) controlling sequence, such that a register controls an order in which chips are refreshed. In another embodiment, refreshing can be determined based on memory banks within semiconductor memory chips.
A refresh controller of an interface control circuit included in a master memory chip in a semiconductor memory device having only one master memory chip according to one embodiment, has been described above, but the inventive concept is not limited thereto. A refresh controller according to one embodiment may also be included in an interface control circuit ICC included in an interface chip or a buffer chip. Also, as illustrated in
In one embodiment, if a plurality of interface control circuits ICC1 and ICC2 are included as illustrated in
As described above, a refresh controller according to one embodiment may refresh a plurality of semiconductor memory chips sequentially or a random order, thereby preventing noise caused when all the plurality of semiconductor memory chips are refreshed simultaneously from being generated.
The interface control circuit ICC of
If the semiconductor memory module MU of
However, the inventive concept is not limited to the embodiments of
In one embodiment, if each of semiconductor memory devices, such as those included in the semiconductor memory module MU of
Each of the memory controllers MCT of
Each of the memory controllers MCT of
Each of the memory controllers MCT of
Operations of the I/O interface unit IU, the address scrambler AS, and the refresh controller RC illustrated in each of
While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
Claims
1. A semiconductor package comprising:
- a package interface including at least a first pair of terminals,
- a stack of semiconductor chips;
- a plurality of stacks of through substrate vias, each stack of through substrate vias comprising plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip; and
- an interface circuit including an input connected to the first pair of terminals to receive a differential signal providing first information, and including an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias.
2. The semiconductor package of claim 1, wherein the interface circuit includes an input buffer including the input and the output.
3. The semiconductor package of claim 1, wherein the interface circuit is configured to provide the output signal as a single-ended signal to at least two of the plurality of stacks of through substrate vias.
4. The semiconductor package of claim 1, wherein the interface circuit is configured to provide the output signal as a single-ended signal to only one stack of through substrate vias.
5. The semiconductor package of claim 1, wherein the interface circuit is configured to interpret the differential signal as a multi-level signal, and to output the single-ended signal based on the interpreted multi-level signal.
6. The semiconductor package of claim 1, wherein the interface circuit is configured to receive data at a first frequency from the first pair of terminals and to output data at a second frequency, lower than the first frequency.
7. The semiconductor package of claim 6, wherein the interface circuit includes a deserializer to receive first data as multiple sequential packets from the pair of terminals and to output the first data in parallel to at least two of the plurality of stacks of through substrate vias.
8. The semiconductor package of claim 7, wherein the first frequency is a multiple of 2n of the second frequency, wherein n is an integer.
9. The semiconductor package of claim 1, wherein the interface circuit is part of one of the semiconductor chips forming the stack of semiconductor chips.
10. The semiconductor package of claim 9, wherein the package comprises only two semiconductor chips.
11. The semiconductor package of claim 1, further comprising:
- a package substrate on which the stack of semiconductor chips is disposed,
- wherein the interface circuit is part of the package substrate.
12. The semiconductor package of claim 1, wherein at least one stack of the plurality of stacks of through substrate vias extends through the entire stack of semiconductor chips.
13. The semiconductor package of claim 1, further comprising:
- one or more single terminals included in the package interface, the one or more single terminals connected to an input to receive one or more respective single-ended input signals, wherein the differential signal is a data signal, and the one or more respective single-ended input signals are not data signals.
14. The semiconductor package of claim 1, further comprising:
- a non-conductive encapsulant covering a top and side portions of the stack of semiconductor chips.
15. A semiconductor package comprising:
- a package interface including at least a first pair of terminals,
- a stack of semiconductor chips;
- a plurality of stacks of through substrate vias, each stack of through substrate vias comprising plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip; and
- an interface circuit including an input connected to the first pair of terminals to receive a differential input signal providing first information, and including an output to provide a differential output signal including the first information in a differential signal format to at least one of the plurality of stacks of through substrate vias.
16. The semiconductor package of claim 15, wherein the interface circuit includes an input buffer including the input and the output.
17. The semiconductor package of claim 15, wherein the interface circuit is configured to provide the differential output signal as a differential signal to at least two of the plurality of stacks of through substrate vias.
18. The semiconductor package of claim 15, wherein the interface circuit is configured to provide the differential output signal as a differential signal to only one stack of through substrate vias.
19. The semiconductor package of claim 15, wherein the interface circuit is configured to interpret the differential input signal as a multi-level signal, and to output the differential output signal based on the interpreted multi-level signal.
20. The semiconductor package of claim 15, wherein the interface circuit is configured to receive data at a first frequency from the first pair of terminals and to output data at a second frequency, lower than the first frequency.
21. The semiconductor package of claim 20, wherein the interface circuit includes a deserializer to receive first data as multiple sequential packets from the pair of terminals and to output the first data in parallel to at least two of the plurality of stacks of through substrate vias.
23. The semiconductor package of claim 22, wherein the first frequency is a multiple of 2n of the second frequency, wherein n is an integer.
24. The semiconductor package of claim 15, wherein the interface circuit is part of one of the semiconductor chips forming the stack of semiconductor chips.
25. The semiconductor package of claim 24, wherein the package comprises only two semiconductor chips.
26. The semiconductor package of claim 15, further comprising:
- a package substrate on which the stack of semiconductor chips is disposed,
- wherein the interface circuit is part of the package substrate.
27. The semiconductor package of claim 15, wherein at least one stack of the plurality of stacks of through substrate vias extends through the entire stack of semiconductor chips.
28. The semiconductor package of claim 15, further comprising:
- one or more single terminals included in the package interface, the one or more single terminals connected to an input to receive one or more respective single-ended input signals, wherein the differential input signal is a data signal, and the one or more respective single-ended input signals are not data signals.
29. The semiconductor package of claim 15, further comprising:
- a non-conductive encapsulant covering a top and side portions of the stack of semiconductor chips.
30. A semiconductor package comprising:
- a package interface including at least a first pair of terminals,
- a stack of semiconductor chips;
- a plurality of stacks of through substrate vias, each stack of through substrate vias comprising plural through substrate vias of respective ones of the semiconductor chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent semiconductor chip; and
- an interface circuit including an input connected to the first pair of terminals to receive a differential input signal providing first information, and including an output to provide an output signal including the first information to at least one of the plurality of stacks of through substrate vias,
- wherein the interface circuit is configured to interpret the differential input signal as a multi-level signal, and to provide the output signal based on the interpreted multi-level signal.
31. The semiconductor package of claim 30, wherein the interface circuit includes an input buffer including the input and the output.
32. The semiconductor package of claim 30, wherein the interface circuit is configured to provide the output signal as a single-ended signal to at least two of the plurality of stacks of through substrate vias.
33. The semiconductor package of claim 30, wherein the interface circuit is configured to provide the output signal as a single-ended signal to only one stack of through substrate vias.
34. The semiconductor package of claim 30, wherein the interface circuit is configured to provide the output signal as a differential signal to at least two of the plurality of stacks of through substrate vias.
35. The semiconductor package of claim 30, wherein the interface circuit is configured to receive data at a first frequency from the first pair of terminals and to output data at a second frequency, lower than the first frequency.
36. The semiconductor package of claim 35, wherein the interface circuit includes a deserializer to receive first data as multiple sequential packets from the pair of terminals and to output the first data in parallel to at least two of the plurality of stacks of through substrate vias.
37. The semiconductor package of claim 36, wherein the first frequency is a multiple of 2n of the second frequency, wherein n is an integer.
38. The semiconductor package of claim 30, wherein the interface circuit is part of one of the semiconductor chips forming the stack of semiconductor chips.
39. The semiconductor package of claim 38, wherein the package comprises only two semiconductor chips.
40. The semiconductor package of claim 30, further comprising:
- a package substrate on which the stack of semiconductor chips is disposed,
- wherein the interface circuit is part of the package substrate.
41. The semiconductor package of claim 30, wherein at least one stack of the plurality of stacks of through substrate vias extends through the entire stack of semiconductor chips.
42. The semiconductor package of claim 30, further comprising:
- one or more single terminals included in the package interface, the one or more single terminals connected to an input to receive one or more respective single-ended input signals, wherein the differential input signal is a data signal, and the one or more respective single-ended input signals are not data signals.
43. The semiconductor package of claim 30, further comprising:
- a non-conductive encapsulant covering a top and side portions of the stack of semiconductor chips.
44. A semiconductor package comprising:
- package terminals connectable to an address bus;
- a stack of memory chips;
- an interface circuit, comprising: an address buffer connected to the package terminals to receive an external address, an address translation circuit connected to receive the external address from the address buffer, and having an output of an internal address, and a monitoring circuit configured to monitor an amount of access operations to at least one memory location of the stack of memory chips and provide a corresponding monitoring result; and
- a plurality of stacks of through substrate vias, each stack of through substrate vias comprising plural through substrate vias of respective ones of the memory chips of the stack, each through substrate via electrically connected to a through substrate via of a immediately adjacent memory chip, each stack of through substrate vias connected to receive the internal address at the output of the address translation circuit;
- wherein the address translation circuit is configured to translate the external address to an internal address in response to at least the monitoring result of the monitoring circuit.
45. The semiconductor package of claim 44, wherein the stack of memory chips comprises a stack of volatile memory chips, and wherein the monitoring circuit monitors a frequency of writing to memory locations of the volatile memory chips of the stack of memory chips.
46. The semiconductor package of claim 45, wherein the volatile memory chips comprise DRAM chips.
47. The semiconductor package of claim 44, wherein the monitoring circuit monitors a frequency of access of memory locations of the memory chips of the stack of memory chips.
48. The semiconductor package of claim 44, wherein the monitoring circuit counts a number of sequential writes to the at least one memory location.
49. A semiconductor package comprising:
- package terminals;
- a stack of memory chips;
- an interface circuit, comprising: an address buffer connected to the package terminals to receive an external address, and an address translation circuit connected to receive the external address from the address buffer, and having an output that outputs an internal address;
- a plurality of stacks of through substrate vias, each stack of through substrate vias comprising plural through substrate vias of respective ones of the memory chips each electrically connected to a through substrate via of an immediately adjacent memory chip, each stack of the plurality of stacks of through substrate vias connected to receive an internal address at the output of the address translation circuit; and
- the interface circuit comprising a refresh controller in logical communication with the package terminals and configured to receive an external refresh control signal, the refresh controller operable to output a series of internal refresh control signals, each of the series of internal refresh control signals operable to initiate a memory refresh of different parts of the stack of memory chips.
50. The semiconductor package of claim 49, wherein each different part of the stack of memory chips comprises a single memory chip.
51. The semiconductor package of claim 49, wherein each different part of the stack of memory chips comprises plural memory chips.
52. The semiconductor package of claim 49, wherein each internal refresh control signal is a refresh code.
53. The semiconductor package of claim 49, wherein each internal refresh control signal is a refresh code and chip address.
54. The semiconductor package of claim 49, wherein the stack of memory chips comprises one of: a stack of PRAM chips, a stack of DRAM chips, and an stack of RRAM chips.
55. The semiconductor package of claim 49, wherein the stack of memory chips comprises only DRAM chips directly stacked on one another.
56. A method of refreshing a stack of memory chips in a semiconductor package, comprising:
- receiving a single external refresh command; and
- in response to the single external refresh command, refreshing first and second chips of the stack of memory chips in sequential order.
57. The method of claim 56, further comprising:
- completing refreshing of the first chip prior to beginning refreshing the second chip.
58. The method of 56, further comprising:
- beginning refreshing of the second chip while refreshing the first chip.
59. The method of 56, wherein the first chip is located closer to a package substrate than the second chip, and the sequential order includes completing refreshing of the first chip prior to completing refreshing of the second chip.
60. The method of 56, further comprising:
- refreshing third and fourth chips of the stack of memory chips in sequential order, wherein the first, second, third, and fourth chips are stacked in sequential order from first to fourth, and are refreshed in sequential order from first to fourth.
61. A semiconductor package comprising:
- a package interface including package terminals including at least a first pair of terminals,
- a stack of memory chips;
- a plurality of stacks of through substrate vias, each stack of through substrate vias comprising plural through substrate vias of respective ones of the memory chips, each through substrate via electrically connected to a through substrate via of an immediately adjacent memory chip; and
- an interface circuit including: an input connected to the first pair of terminals to receive a differential signal providing first information, and including an output to provide an output signal including the first information in a single-ended signal format to at least one of the plurality of stacks of through substrate vias an address buffer connected to a plurality of the package terminals to receive an external address, an address translation circuit connected to receive the external address from the address buffer, and having an output of an internal address, a monitoring circuit configured to monitor an amount of access operations to at least one memory location of the stack of memory chips and provide a corresponding monitoring result, and a refresh controller in logical communication with a plurality of the package terminals and configured to receive an external refresh control signal, the refresh controller operable to output a series of internal refresh control signals, each of the series of internal refresh control signals operable to initiate a memory refresh of different parts of the stack of memory chips, wherein the address translation circuit is configured to translate the external address to an internal address in response to at least the monitoring result of the monitoring circuit.
62. The semiconductor package of claim 61, wherein the interface circuit is configured to provide the output signal as a single-ended signal to at least two of the plurality of stacks of through substrate vias.
63. The semiconductor package of claim 61, wherein the interface circuit is configured to provide the output signal as a single-ended signal to only one stack of through substrate vias.
64. The semiconductor package of claim 61, wherein the interface circuit is configured to interpret the differential signal as a multi-level signal, and to output the single-ended signal based on the interpreted multi-level signal.
65. The semiconductor package of claim 61, wherein the stack of memory chips comprises a stack of volatile memory chips, and wherein the monitoring circuit monitors a frequency of writing to memory locations of the volatile memory chips of the stack of memory chips.
66. The semiconductor package of claim 61, wherein the monitoring circuit monitors a frequency of access of memory locations of the memory chips of the stack of memory chips.
67. The semiconductor package of claim 61, wherein each different part of the stack of memory chips comprises a single memory chip.
68. The semiconductor package of claim 61, wherein each different part of the stack of memory chips comprises plural memory chips.
Type: Application
Filed: Aug 12, 2011
Publication Date: Mar 8, 2012
Patent Grant number: 8885380
Inventors: Uk-song Kang (Seongnam-si), Young-hyun Jun (Seoul), Joo-sun Choi (Yongin-si)
Application Number: 13/209,026
International Classification: G06F 12/10 (20060101); G11C 7/00 (20060101); H01L 23/48 (20060101);