Abstract: A lane keeping assistance system (LKAS) is a system that detects a lane through a sensor and prevents a vehicle from deviating from the lane by changing positional information of the detected lane to a torque value. Disclosed are an apparatus and a method for controlling lane keeping of a vehicle that start or cancel a lane keeping function based on driving state of the vehicle.

Abstract: A display device according to an exemplary embodiment of the present invention includes a display panel displaying an image, a window positioned on the display panel and protecting the display panel, and a protection film attached under the display panel and reflecting light transmitted from the outside. The protection film may comprise a first base layer, a metal layer positioned on the first base layer, and, optionally, a second base layer formed on the metal layer. The base layers may be formed of an organic polymer, and the metal layer may be formed of a metal that imparts light reflectivity. A method for manufacturing such a display device is also presented.

Abstract: A display device according to an exemplary embodiment of the present invention includes a display panel displaying an image, a window positioned on the display panel and protecting the display panel, and a protection film attached under the display panel and reflecting light transmitted from the outside. The protection film may comprise a first base layer, a metal layer positioned on the first base layer, and, optionally, a second base layer formed on the metal layer. The base layers may be formed of an organic polymer, and the metal layer may be formed of a metal that imparts light reflectivity. A method for manufacturing such a display device is also presented.

Abstract: Disclosed is a lane keeping control system, including: a target distance calculator configured to calculate a target distance by receiving a speed of a vehicle; and a target trace generator configured to generate coordinates of a target point separated by the target distance by receiving vehicle information and camera image information and generate a target trace to the target point as a circular trace. Accordingly, by variably calculating a target distance according to a speed of a vehicle, generating a target trace of a vehicle according to the target distance as a profile (curvature) in a form of a circular trace, and applying the generated profile (curvature) to a lane keeping control, smooth lane keeping control may be achieved and a sense of steering difference of a driver may be minimized.

Abstract: A semiconductor memory device includes a mode control circuit configured to output a DLL on signal which is periodically activated during a specific mode; and a DLL circuit configured to delay and lock a clock to generate a DLL clock, and to be periodically turned on in response to the DLL on signal during the start of the specific mode.

Abstract: In an integrated circuit device and method of manufacturing the same, a conductive structure and a wiring structure are sequentially arranged on a substrate having a through hole. The conductive structure includes semiconductor chips and a contact structure. The wiring structure includes a metal line through which signals are transferred to the conductive structure. A penetration electrode is positioned in the through hole. The penetration electrode includes a conductive plug electrically connected to one of the conductive structure and the wiring structure, and a pair of a base layer and a gap interposed between the conductive plug and a sidewall of the through-hole, thereby enclosing the conductive plug. The base layer also includes a product of a solid reaction of reactants of which diffusion speeds are different. Accordingly, the dielectric characteristics of the penetration electrode are improved by using the gap as a dielectric gap.

Abstract: A semiconductor wet etchant includes deionized water, a fluorine-based compound, an oxidizer and an inorganic salt. A concentration of the fluorine-based compound is 0.25 to 10.0 wt % based on a total weight of the etchant, a concentration of the oxidizer is 0.45 to 3.6 wt % based on a total weight of the etchant, and a concentration of the inorganic salt is 1.0 to 5.0 wt % based on a total weight of the etchant. The inorganic salt comprises at least one of an ammonium ion (NH4+) and a chlorine ion (Cl?).

Abstract: A semiconductor wet etchant includes deionized water, a fluorine-based compound, an oxidizer and an inorganic salt. A concentration of the fluorine-based compound is 0.25 to 10.0 wt % based on a total weight of the etchant, a concentration of the oxidizer is 0.45 to 3.6 wt % based on a total weight of the etchant, and a concentration of the inorganic salt is 1.0 to 5.0 wt % based on a total weight of the etchant. The inorganic salt comprises at least one of an ammonium ion (NH4+) and a chlorine ion (Cl?).

Abstract: There is provided an inkjet head including: a flow path plate having a plurality of ink chambers; a nozzle plate having a plurality of nozzles connected to the respective ink chambers in order to eject ink in the ink chambers to the outside; a piezoelectric actuator provided above the ink chambers and controlling pressure of the ink chambers; and a parylene protective film provided in order to prevent oxidization of the piezoelectric actuator.

Abstract: A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control signal; a second clock buffer for outputting a second internal clock signal in response to the system clock signal and for correcting a duty cycle ratio of the second internal clock signal in response to the control signal; an analog duty cycle correction circuit for outputting the control signal corresponding to the duty cycle ratio of the first and second internal clock signals; a mixing circuit for mixing the first and second internal clock signals and for outputting a third internal clock signal whose duty cycle is corrected; and a DLL circuit for outputting a delay-locked clock signal by using the third internal clock signal.

Abstract: A memory device may include a cathode, an anode, a link connected to the anode, and a first connection element that connects the link to the cathode. The link and the anode may be located in a position lower than that of the cathode or the link and the anode may be located in a position higher than that of the cathode. Also, the cathode, the anode, the link, and the first connection element may be formed on the same plane.

Abstract: A delay locked loop includes a buffer for outputting an internal clock by buffering an external clock, a delay block for delaying the internal clock in response to one of control signals or a selection signal, thereby outputting a delayed clock, a control signal generation block for generating at least one control signal according to a phase difference between the internal clock and a feedback clock generated by delaying the delayed clock by a delay time taken for the internal clock to be output, a selection block for outputting at least one selection signal in response to a signal instructing an off mode of the delay locked loop, thereby controlling a delay time in the delay block, and an output driver for driving the delayed clock.

Abstract: A delay locked loop includes a DLL hold control unit that receives a first control signal and outputs a DLL hold control signal, and a DLL block that receives the DLL hold control signal and generates a DLL clock.

Abstract: A semiconductor memory device comprises a plurality of banks, each having first and second cell mats, each having a plurality of word lines; a data access controller for selecting a word line from the first cell mat and the second cell mat in response to the row address and a refresh signal to be used in a refresh operation; and a bank controller for sequentially enabling the first cell mat and the second cell mat in response to a bank address and the refresh signal.

Abstract: A DLL (Delay Locked Loop) clock signal generating circuit includes a duty correction buffer for receiving a first clock signal and a second clock signal, producing a first internal clock signal and a second internal clock signal, and correcting duty ratios of the first and second internal clock signals based on a reference signal which is controlled by a duty ratio of the first internal clock signal, and an edge trigger unit for a DLL clock signal which has a first level when the first internal clock signal is activated and which has a second level when the second internal clock signal is activated.

Abstract: A semiconductor memory device includes a mode control circuit configured to output a DLL on signal which is periodically activated during a specific mode; and a DLL circuit configured to delay and lock a clock to generate a DLL clock, and to be periodically turned on in response to the DLL on signal during the start of the specific mode.

Abstract: A semiconductor device may include a decoder for decoding a plurality of internal command signals and outputting a first Y-address enabling signal; a Y-address enabling signal generator for receiving the first Y-address enabling signal and outputting a second Y-address enabling signal having a predetermined enabled period; a multiplexer (MUX) for receiving the first Y-address enabling signal and the second Y-address enabling signal and selectively outputting any one thereof as a Y-address enabling signal; and a MUX controller for controlling the MUX such that the MUX selects any one of the first Y-address enabling signal or second Y-address enabling signal according to an operation mode of the semiconductor device.

Abstract: Provided are an electrical fuse device and a method of operating the same. The electrical fuse device may include a fuse link having a multi layer structure with at least two metal layers. The number of metal layers that are blown, from among the at least two metal layers, may vary according to either the duration of application of voltage or the strength of voltage applied.

Abstract: A memory device may include a cathode, an anode, a link connected to the anode, and a first connection element that connects the link to the cathode. The link and the anode may be located in a position lower than that of the cathode or the link and the anode may be located in a position higher than that of the cathode. Also, the cathode, the anode, the link, and the first connection element may be formed on the same plane.

Abstract: A DLL (Delay Locked Loop) clock signal generating circuit includes a duty correction buffer for receiving a first clock signal and a second clock signal, producing a first internal clock signal and a second internal clock signal, and correcting duty ratios of the first and second internal clock signals based on a reference signal which is controlled by a duty ratio of the first internal clock signal, and an edge trigger unit for a DLL clock signal which has a first level when the first internal clock signal is activated and which has a second level when the second internal clock signal is activated.