Patents by Inventor Young Jin JUNG

Young Jin JUNG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998477
    Abstract: A polyester resin composition includes: (A) polycyclohexylenedimethylene terephthalate (PCT) resin which is a polymer of terephthalic acid and cyclohexanedimethanol, wherein the cyclohexanedimethanol has a trans/cis isomer ratio of about 2.3 or more; (B) a white pigment, wherein the white pigment is titanium dioxide; and (C) inorganic fillers, wherein the inorganic fillers are glass fibers. A molded article formed from the polyester resin composition can exhibit improved mechanical properties and moldability, and thus can be suitable for light emitting diode (LED) reflectors.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: May 4, 2021
    Assignee: Lotte Chemical Corporation
    Inventors: Tae Gon Kang, Chan Moo Park, Yoo Jin Jung, Jong Cheol Lim, Sang Hyun Hong, Tae Soo Kim, Young Ho Park
  • Patent number: 10957708
    Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and the connection region, a plurality of channel structures passing through the plurality of gate electrodes and extending in a vertical direction in the memory cell region, and a plurality of pad layers extending in a first direction from each of the plurality of gate electrodes in the connection region. The plurality of pad layers is disposed in a stepped form in a second direction. The device further includes a plurality of dummy lines arranged in one row in the first direction between two pad layers adjacent to each other in the second direction and disposed apart from one another with a pad connection region therebetween in the first direction. The pad connection region overlaps two pad layers successively disposed in the first direction.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: March 23, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Jin Jung, So-Ra Kim, Bong-Tae Park
  • Patent number: 10950619
    Abstract: A semiconductor memory device includes a substrate including a cell array region and a pad region, a stack structure disposed on the cell array region and the pad region of the substrate and including gate electrodes, a device isolation layer vertically overlapping the stack structure and disposed in the pad region of the substrate, a dummy vertical channel portion penetrating the stack structure on the pad region of the substrate and disposed in the device isolation layer, and a dummy semiconductor pillar disposed between the dummy vertical channel portion and one portion of the substrate being in contact with one sidewall of the device isolation layer.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young-Jin Jung, Sunghan Cho
  • Publication number: 20210074724
    Abstract: A three-dimensional semiconductor memory device and a method of manufacturing the same. The device may include a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, a plurality of first vertical structures penetrating the electrode structures on the cell array region, and a plurality of second vertical structures penetrating the electrode structures on the connection region. Each of the first and second vertical structures may include a lower semiconductor pattern connected to the substrate and an upper semiconductor pattern connected to the lower semiconductor pattern.
    Type: Application
    Filed: October 19, 2020
    Publication date: March 11, 2021
    Inventors: JONGWON KIM, Young-Jin Jung
  • Publication number: 20210054742
    Abstract: A compressor vane is provided. The compressor vane may include a first surface directed toward air introduced into a compressor, a second surface directed in a direction opposite to the first surface, and two tangent lines in which the first and second surfaces meet, wherein a rate of change, with respect to a height of the compressor vane, of a maximum separation distance, between the first surface and the second surface, divided by a distance from one to the other of the two tangent lines in a cross-section at one position of the height of the compressor vane in a direction starting from a portion of the compressor vane closest to a center tie rod and toward a compressor housing varies with the height of the compressor vane away from the portion of the compressor vane closest to the center tie rod.
    Type: Application
    Filed: June 8, 2020
    Publication date: February 25, 2021
    Inventors: Young Jin JUNG, Jun Hyuk SEO, Sung Ryong LEE, Jae Woo CHOI
  • Patent number: 10923489
    Abstract: A three-dimensional semiconductor device is provided including a gate electrode disposed on a substrate and having a pad region, a cell vertical structure passing through the gate electrode, a dummy vertical structure passing through the pad region, and a gate contact plug disposed on the pad region. The cell vertical structure includes a cell pad layer disposed on a level higher than that of the gate electrode and a cell channel layer opposing the gate electrode, the dummy vertical structure includes a buffer region formed of a material different from that of the cell pad layer and a dummy channel layer formed of a material the same as that of the cell channel layer, and at least a portion of the buffer region is located on the same plane as at least a portion of the cell pad layer.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Young Jin Jung
  • Publication number: 20210036009
    Abstract: A nonvolatile memory device with improved operation performance and reliability, and a method for fabricating the same are provided. The nonvolatile memory device includes a substrate, a peripheral circuit structure on the substrate, a mold structure including a plurality of insulating patterns and a plurality of gate electrodes stacked alternately on the peripheral circuit structure, a channel structure penetrating the mold structure, a first impurity pattern in contact with first portions of the channel structure and having a first conductivity type, on the mold structure, and a second impurity pattern in contact with second portions of the channel structure and having a second conductivity type different from the first conductivity type, on the mold structure.
    Type: Application
    Filed: March 13, 2020
    Publication date: February 4, 2021
    Inventors: Young-Jin JUNG, Bong Tae PARK, Ho Jun SEONG
  • Publication number: 20200385846
    Abstract: The present disclosure relates to wear-resistant steel comprising, by weight, carbon (C): 0.19 to 0.28%, silicon (Si): 0.1 to 0.7%, manganese (Mn): 0.6 to 1.6%, phosphorus (P): 0.05% or less, sulfur (S): 0.02% or less, aluminum (Al): 0.07% or less, chromium (Cr): 0.01 to 0.5%, nickel (Ni): 0.01 to 3.0%, copper (Cu): 0.01 to 1.5%, molybdenum (Mo): 0.01 to 0.5%, boron (B): 50 ppm or less, and cobalt (Co): 0.02% or less, further comprising one or more selected from the group consisting of titanium (Ti): 0.02% or less, niobium (Nb): 0.05% or less, vanadium (V): 0.05% or less, and calcium (Ca): 2 to 100 ppm, and comprising a remainder of iron (Fe) and other unavoidable impurities, wherein C, Ni, and Cu satisfy the following relationship 1, wherein a microstructure includes 97 area % or more of martensite: C×Ni×Cu?0.05.
    Type: Application
    Filed: December 21, 2018
    Publication date: December 10, 2020
    Inventors: Seng-Ho YU, Young-Jin JUNG, Yong-Woo KIM
  • Publication number: 20200381453
    Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Sung-Yun LEE, Jae-Hoon JANG, Jae-Duk LEE, Joon-Hee LEE, Young-Jin JUNG
  • Patent number: 10818687
    Abstract: A three-dimensional semiconductor memory device and a method of manufacturing the same. The device may include a substrate including a cell array region and a connection region, an electrode structure including electrodes vertically stacked on the substrate, a plurality of first vertical structures penetrating the electrode structures on the cell array region, and a plurality of second vertical structures penetrating the electrode structures on the connection region. Each of the first and second vertical structures may include a lower semiconductor pattern connected to the substrate and an upper semiconductor pattern connected to the lower semiconductor pattern.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: October 27, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongwon Kim, Young-Jin Jung
  • Patent number: 10811356
    Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality of bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jin Jung, Joon-hee Lee
  • Patent number: 10770473
    Abstract: A vertical type semiconductor device includes insulation patterns on a substrate and spaced apart from each other in a first direction perpendicular to a top surface of the substrate, a channel structure on the substrate and penetrating through the insulation patterns, a first conductive pattern partially filling a gap between the insulation patterns adjacent to each other in the first direction and the channel structure and having a slit in a surface thereof, the slit extending in a direction parallel with the top surface of the substrate, and a second conductive pattern on the first conductive pattern in the gap and filling the slit.
    Type: Grant
    Filed: September 5, 2018
    Date of Patent: September 8, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Yun Lee, Jae-Hoon Jang, Jae-Duk Lee, Joon-Hee Lee, Young-Jin Jung
  • Publication number: 20200183371
    Abstract: An automated guided vehicle control system includes an automated guided vehicle (AGV) transporting parts by moving along a guide line designed on a floor of a factory; and a server displaying a guide line map of the factory on a screen through an AGV path setting UI, setting a transport path of the AGV depending on selection of a node which is present in the guide line and AGV motion information considering a link direction between neighboring nodes included in the transport path and transmitting the set transport path and motion information to the AGV through a wireless relay.
    Type: Application
    Filed: June 6, 2019
    Publication date: June 11, 2020
    Applicants: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION
    Inventors: Kyung Dong PARK, Young Jin Jung, Sang Won Yoon
  • Publication number: 20200176375
    Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality of bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.
    Type: Application
    Filed: February 7, 2020
    Publication date: June 4, 2020
    Inventors: Young-jin Jung, Joon-hee Lee
  • Publication number: 20200168621
    Abstract: A three-dimensional semiconductor device is provided including a gate electrode disposed on a substrate and having a pad region, a cell vertical structure passing through the gate electrode, a dummy vertical structure passing through the pad region, and a gate contact plug disposed on the pad region. The cell vertical structure includes a cell pad layer disposed on a level higher than that of the gate electrode and a cell channel layer opposing the gate electrode, the dummy vertical structure includes a buffer region formed of a material different from that of the cell pad layer and a dummy channel layer formed of a material the same as that of the cell channel layer, and at least a portion of the buffer region is located on the same plane as at least a portion of the cell pad layer.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 28, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Young Jin JUNG
  • Publication number: 20200144287
    Abstract: A semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and the connection region, a plurality of channel structures passing through the plurality of gate electrodes and extending in a vertical direction in the memory cell region, and a plurality of pad layers extending in a first direction from each of the plurality of gate electrodes in the connection region. The plurality of pad layers is disposed in a stepped form in a second direction. The device further includes a plurality of dummy lines arranged in one row in the first direction between two pad layers adjacent to each other in the second direction and disposed apart from one another with a pad connection region therebetween in the first direction. The pad connection region overlaps two pad layers successively disposed in the first direction.
    Type: Application
    Filed: July 24, 2019
    Publication date: May 7, 2020
    Inventors: YOUNG-JIN JUNG, SO-RA KIM, BONG-TAE PARK
  • Publication number: 20200083250
    Abstract: A three-dimensional semiconductor device includes: a common source line passing between a first channel structure and a second channel structure and between a first dummy channel structure and a second dummy channel structure, in which a distance in a first direction between the common source line and the first channel structure is equal to a distance in the first direction between the common source line and the second channel structure, and a distance in the first direction between the common source line and the first dummy channel structure is different from a distance in the first direction between the common source line and the second dummy channel structure.
    Type: Application
    Filed: April 15, 2019
    Publication date: March 12, 2020
    Inventors: YOUNG-JIN JUNG, Hyoung-ryeol In, Sung-han Cho
  • Patent number: 10586766
    Abstract: Provided is an integrated circuit device including a plurality of word lines overlapping each other, in a vertical direction, on a substrate, a plurality of channel structures extending in the vertical direction through the plurality of word lines on an area of the substrate, a plurality of bit line contact pads on the plurality of channel structures, and a plurality of bit lines, wherein the plurality of bit lines include a plurality of first bit lines extending parallel to each other at a first pitch in a center region of the area, and a plurality of second bit lines extending at a second pitch in an edge region of the area, the second pitch being different from the first pitch.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: March 10, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jin Jung, Joon-hee Lee
  • Patent number: 10553598
    Abstract: A three-dimensional semiconductor device is provided including a gate electrode disposed on a substrate and having a pad region, a cell vertical structure passing through the gate electrode, a dummy vertical structure passing through the pad region, and a gate contact plug disposed on the pad region. The cell vertical structure includes a cell pad layer disposed on a level higher than that of the gate electrode and a cell channel layer opposing the gate electrode, the dummy vertical structure includes a buffer region formed of a material different from that of the cell pad layer and a dummy channel layer formed of a material the same as that of the cell channel layer, and at least a portion of the buffer region is located on the same plane as at least a portion of the cell pad layer.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: February 4, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Young Jin Jung
  • Publication number: 20190390293
    Abstract: The present invention relates to wear-resistant steel used in construction machines, among others, and more specifically, to high-hardness wear-resistant steel having excellent wear resistance to a thickness of 40 to 130t (mm) as well as high strength and impact toughness, and to a method for manufacturing the high-hardness wear-resistant steel.
    Type: Application
    Filed: December 4, 2017
    Publication date: December 26, 2019
    Inventors: Seng-Ho YU, Mun-Young JUNG, Young-Jin JUNG