Abstract: A portable player may include a control unit designed to perform an instant replay operation using instant replay data stored in a nonvolatile semiconductor memory during a cold boot operation. The control unit may be designed to perform the instant replay operation without accessing a mechanical mass storage device during the cold boot operation, and the instant replay data may be loaded from a volatile work memory to the nonvolatile semiconductor memory during a power-down conversion.

Abstract: A flash memory device comprises a non-volatile memory core operatively connected to first and second buffer memories through a page buffer. The device further comprises a first register adapted to receive command and address information from a host system, a copy circuit adapted to copy the command and address information from the first register to a second register within a control logic circuit. The device alternately transfers information to the first and second buffer memories during a cache read operation comprising a plurality of data read operations.

Abstract: A memory may include first and second buffer memories and a memory core. The memory core may include memory blocks each having a plurality of pages and a page buffer for reading data from a selected memory block. A control logic may control the first and second buffer memories and the memory core. The control logic may have a register for storing address and command information of the memory core. The control logic may control the memory core so that data read periods for pages of the selected memory block are carried out according to the stored address and command information. The control logic may control the first and second buffer memories and the memory core so that data in the page buffer may be transferred to the first and/or second buffer memories during the data read periods.

Abstract: A hard disk drive is disclosed and related methods of reading/writing data are disclosed. The hard disk drive includes a disk serving as a main data storage medium, and first and second buffers storing data to be stored on the disk, as well as a controller defining a data I/O path in relation to a detected operating state of the hard disk drive.

Abstract: A non-volatile semiconductor memory device includes memory blocks and an erase controller configured to control a multi-block erase operation where at least two of the memory blocks are simultaneously erased. According to some embodiments, after selecting and simultaneously erasing the selected memory blocks, an erase verify operation for each of the erased memory blocks is performed according to an externally provided erase verify command and block address. According to some embodiments, if a suspend command is received by the memory device while selected memory blocks are being erased, the erase operation ceases and another operation, such as a read operation, begins. When a resume command is received by the memory device, the erase operation resumes. Other embodiments are described and claimed.

Abstract: There is provided an apparatus for controlling a flash memory, which includes a memory for storing a plurality of flash translation layers; and a control block for, when an access is requested from outside, determining a pattern of the access, selecting one of the flash translation layers stored in the memory based on the determination result, and managing mapping data of the flash memory based on the selected flash translation layer.

Abstract: Method of programming nonvolatile memory devices are provided in which data is programmed into a first plurality of memory cells of the nonvolatile memory device. At the same time associated programming confirmation information is programmed into at least one second memory cell of the nonvolatile memory device. Then, a determination is made as to whether the data was correctly programmed into the first plurality of memory cells based on an evaluation of (1) the threshold voltage distributions of at least some of the first plurality of memory cells and (2) the threshold voltage distribution of the at least one second memory cell. Methods of resuming a data programming operation after an interruption such as a loss of power are also provided.

Abstract: Provided are a portable storage device and a method of data recovery using the same, in which when the integrity of the recorded data is damaged, the integrity of the recorded data can be easily recovered. The portable storage device includes a memory unit that stores predetermined recovery information for the recorded data, a determining unit that determines whether a device that accesses the recorded data supports the stored recovery information, and a control unit that selectively recovers the recorded data using the stored recovery information based on a result of the determination.

Abstract: Method of programming nonvolatile memory devices are provided in which data is programmed into a first plurality of memory cells of the nonvolatile memory device. At the same time associated programming confirmation information is programmed into at least one second memory cell of the nonvolatile memory device. Then, a determination is made as to whether the data was correctly programmed into the first plurality of memory cells based on an evaluation of (1) the threshold voltage distributions of at least some of the first plurality of memory cells and (2) the threshold voltage distribution of the at least one second memory cell. Methods of resuming a data programming operation after an interruption such as a loss of power are also provided.

Abstract: A non-volatile semiconductor memory device includes memory blocks and an erase controller configured to control a multi-block erase operation where at least two of the memory blocks are simultaneously erased. According to some embodiments, after selecting and simultaneously erasing the selected memory blocks, an erase verify operation for each of the erased memory blocks is performed according to an externally provided erase verify command and block address. According to some embodiments, if a suspend command is received by the memory device while selected memory blocks are being erased, the erase operation ceases and another operation, such as a read operation, begins. When a resume command is received by the memory device, the erase operation resumes. Other embodiments are described and claimed.

Abstract: A multiple chip memory system capable of providing state information relating to each chip embedded therein. The multiple chip memory system includes a first chip enabled by a first chip selection signal, and informing of a self state by a first ready/busy signal; and a second chip enabled by a second chip selection signal, and informing of a self state by a second ready/busy signal.

Abstract: In one embodiment, a semiconductor device comprises an active region isolated by a device isolation layer placed in a semiconductor substrate having a main surface. A molding hole is placed in the semiconductor substrate on the active region. A pocket insulating layer pattern conformally covers the molding hole. A pocket line extends across the active region, filling the molding hole and protruding from the main surface of the semiconductor substrate. The pocket line includes a pocket conductive layer line, a lower metal layer line, and an upper metal layer line, which are sequentially stacked on the pocket insulating later pattern. The device further may further include a line capping layer pattern placed on the pocket line. The line capping layer pattern and the pocket conductive layer line may surround the lower and upper metal layer lines.

Abstract: The trunk routing device and method in a CDMA mobile communication system according to the present invention is contrived to assign and establish a plurality of trunks in the unit of packet to send packet data between a base station controller and a base transceiver station in order to uniformly utilize all trunk paths. Once receiving a new packet from a node connected to the base station controller, the invention extracts information about the packet designation from every packet and switches the packet data with the trunks connected to the designation in the unit of packet, thus sending the packet date to the base transceiver station.

Abstract: A multiple chip memory system capable of providing state information relating to each chip embedded therein. The multiple chip memory system includes a first chip enabled by a first chip selection signal, and informing of a self state by a first ready/busy signal; and a second chip enabled by a second chip selection signal, and informing of a self state by a second ready/busy signal.

Abstract: A computer system includes a system controller with a central processing unit and a memory bus controller operating in a first interface mode; a system memory connected with the system controller through the system bus; a NAND flash memory for storing a system driving code, an operating system program and user data for the computer system; and an interface unit communicating with the system controller through the system bus in the first interface mode and communicating with the NAND flash memory in a second interface mode, the interface unit being synchronized with a clock signal generated therein in response to predetermined command and operating information. The NAND flash memory may be used for the system bootstrap, and data transmission to the system controller during reading or programming operations is performed successively to reduce the latency time on the read operation and the data loading time on the programming operation.

Abstract: A system and method are provided for booting a computing device using a NAND flash memory. Boot code stored in the NAND flash memory is transferred to a RAM for execution by the CPU. Operating system program stored in the NAND flash memory is transferred to a system memory for execution therefrom by the CPU after system boot.

Abstract: A nonvolatile semiconductor memory device comprises an address buffer, a column address register, a selection circuit, a data input/output circuit, and a controller. The controller controls the column address changes of the memory device during the read/write operation. When external addresses are applied to a first input/output pins while data is transferred from a second input/output pins to an internal register or is transferred from the internal register to the second input/output pins through the data input/output circuit, the control circuit stores the external addresses in the column address register as a column address. A page size of the nonvolatile semiconductor memory device having such a column address change function can be increased irrespective of a memory system.

Abstract: A plurality of nonvolatile memories are adapted to generate ready/busy signals and internal inverted chip enable signals. A controller outputs to the memories an external inverted chip enable signal, an inverted write enable signal, an inverted read enable signal, an address, and data, and inputs the ready/busy signals outputted from the nonvolatile memories. Each of the nonvolatile memories includes a circuit that generates a first read “don't care” signal during a disable interval of an inverted write enable signal and a disable interval of an inverted read enable signal when a read command is applied during a read operation, and a second circuit that generates a second read “don't care” signal that is enabled by detecting an address input end, and disabled by detecting a ready state of a ready/busy signal when the read command is applied during the read operation.

Abstract: A nonvolatile semiconductor memory device comprises an address buffer, a column address register, a selection circuit, a data input/output circuit, and a controller. The controller controls the column address changes of the memory device during the read/write operation. When external addresses are applied to a first input/output pins while data is transferred from a second input/output pins to an internal register or is transferred from the internal register to the second input/output pins through the data input/output circuit, the control circuit stores the external addresses in the column address register as a column address. A page size of the nonvolatile semiconductor memory device having such a column address change function can be increased irrespective of a memory system.

Abstract: A preferred method of programming a multi-flash memory device uses a shared selection signal for the flash memory chips. A first page in a first chip is programmed in a first programming operation. A first page in a second chip is then programmed in a second programming operation. The programmed state of the first chip is checked by inputting a first status command during the second programming operation. A second page in the first chip is programmed in a third programming operation and a programmed state of the second chip can be checked by inputting a second status command during the third programming operation. A second page in the second chip can also be programmed. An improved multi-flash memory system structure is also provided.