Abstract: A dynamic random access memory (DRAM) features an address counter strobe test mode device including a reference pulse generator, an address counter strobe test mode unit, an internal address counter unit, and an address decoding unit. The reference pulse generator receives an external clock signal and generates an internal clock signal. The address counter strobe test mode unit receives the internal clock signal and outputs an address strobe signal, wherein a pulse width and a pulse generating time of the address strobe signal are regulated in response to a plurality of control signals outputted from a mode register set. The internal address counter unit receives an external address signal and outputs an internal address signal in response to the address strobe signal. The address decoding unit decodes the internal address signal. As a result, the address counter strobe test mode device prevents mis-operations caused by mis-addressing in the DRAM.

Abstract: A buffering circuit of a semiconductor memory device is provided with a plurality of buffers divided into groups, comprising: a first controller for generating a first enable signal in response to a refresh signal and a clock enable signal; a second controller for generating a second enable signal in response to an auto-refresh signal and the first enable signal; a first buffer block including at least one of signal input buffers controlled by the first enable signal; and a second buffer block including at least one of signal input buffers controlled by the second enable signal. The groups of the buffers are independently assigned to their corresponding enable signals.

Abstract: The present invention is a high-voltage generation circuit configured to sequentially activate a plurality of high-voltage pump circuits to precisely pump a level of high voltage. In one embodiment, the high-voltage generation circuit includes a high-voltage level detection unit for outputting a high-voltage detected signal, a high-voltage pump control unit for generating a control signal responsive to a detected signal, an oscillator for generating a pulse signal for driving a plurality of high-voltage pumps, a sequential delay unit for sequentially delaying the pulse signal from the oscillator, and a plurality of high-voltage pumps for pumping the high voltage based on a delayed pulse signal and the control signal.

Abstract: A buffering circuit of a semiconductor memory device is provided with a plurality of buffers divided into groups, comprising: a first controller for generating a first enable signal in response to a refresh signal and a clock enable signal; a second controller for generating a second enable signal in response to an auto-refresh signal and the first enable signal; a first buffer block including at least one of signal input buffers controlled by the first enable signal; and a second buffer block including at least one of signal input buffers controlled by the second enable signal. The groups of the buffers are independently assigned to their corresponding enable signals.