Abstract: A semiconductor device and a method of fabricating the same are disclosed. A semiconductor device according to an embodiment of the present invention includes: a first type doped semiconductor substrate; a second type doped deep well configured such that one or more semiconductor device elements are formed therein; a first type doped first well formed inside a region surrounded by the deep well of the one surface of the semiconductor substrate, and separated from the semiconductor substrate by the deep well; a first electrical contact formed on a part of the one surface of the semiconductor substrate, and electrically connected to the first well; and a second electrical contact formed on another surface of the semiconductor substrate.

Abstract: The present invention relates to a composition for forming a hard coating layer, which may form a hard coating layer having significantly improved hardness as well as excellent flexibility such that curling is minimized.

Abstract: A composition for forming a hard coating layer includes an epoxy siloxane resin having a weight average molecular weight in the range of 2,000 to 15,000 and a polydispersity index (PDI) in the range of 2.0 to 4.0, and thus may form a hard coating layer having significantly improved hardness as well as excellent flexibility such that bending deformation is minimized.

Abstract: A method and server for blocking access of an unauthorized device in a wireless communication system are provided. The method of the server includes receiving a report in which at least one unauthorized equipment is detected from at least one sensor; determining the at least one sensor to allocate each of the detected at least one unauthorized equipment based on at least one of a number of the at least one unauthorized equipment and a number of channels allocated to each of the at least one sensor; and requesting access blocking of the at least one unauthorized equipment allocated to a corresponding at least one sensor to the determined at least one sensor.

Abstract: Disclosed are a biomolecular sensor and a method of fabricating the same having high sensitivity and resolution by using a plurality of metal plates that change electrical properties of a plurality of nanostructures according to the attachment of biomolecules. The biomolecular sensor includes a substrate, first and second electrodes disposed to be spaced apart from each other on the substrate, a plurality of nanostructures disposed on the substrate to connect the first and second electrodes to each other, and a plurality of metal plates that change electrical properties of the plurality of nanostructures according to the attachment of biomolecules.

Abstract: A reference potential adjusting apparatus is provided. The reference potential adjusting apparatus includes a reference potential measuring unit configured to measure a potential of a solution, a counter electrode disposed in the solution, and configured to change the potential of the solution through oxidation-reduction reactions with the solution, and a comparator configured to compare a measurement voltage provided by the reference voltage measuring unit to a reference voltage provided by a reference voltage supply unit, and to adjust reactions of the counter electrode with the solution according to the result of the comparison. The reference potential measuring unit includes a reference electrode, a common electrode disposed to be spaced apart from the reference electrode, and at least one nano structure contacting the reference electrode and the common electrode, and having electrical conductivity changing according to the potential of the solution.

Abstract: A method of forming a channel layer of an electric device according to an embodiment is provided. First, a conductive substrate including an insulating layer on the substrate is provided. The conductive substrate and a metal to be plated are used as respective electrodes to carry out electroplating within an electrolyte solution. In this case, electrons provided by a tunneling current passing through the insulating layer from the conductive substrate are bonded with ions of the metal within the electrolyte solution to form a metal channel layer on the insulating layer.

Abstract: A memory includes at least one first substrate on which unit memory arrays are disposed as a matrix type, each unit memory array including unit memory cells disposed in an array, a second substrate stacked with the at least one first substrate, the second substrate including a sense amplifier region in which sense amplifiers configured to sense information stored in the unit memory cells are disposed, and a plurality of vertical conduction traces configured to electrically connect the at least one first substrate with the second substrate. The sense amplifier region is disposed in a memory region of the second substrate, wherein the memory region of the second substrate corresponds to the memory region of the first substrate.

Abstract: Provided is a flat panel display device. The flat panel display device includes a board unit having a board surface, and a display unit facing the board unit, the display unit having a second surface facing the board surface and a first surface opposite to the second surface and for allowing an image to be displayed thereon, wherein the display unit transmits external light through the first surface and the second surface, to allow the board surface to be seen through the first surface of the display unit.

Abstract: A memory includes at least one first substrate on which unit memory arrays are disposed as a matrix type, each unit memory array including unit memory cells disposed in an array, a second substrate stacked with the at least one first substrate, the second substrate including a sense amplifier region in which sense amplifiers configured to sense information stored in the unit memory cells are disposed, and a plurality of vertical conduction traces configured to electrically connect the at least one first substrate with the second substrate. The sense amplifier region is disposed in a memory region of the second substrate, wherein the memory region of the second substrate corresponds to the memory region of the first substrate.

Abstract: A method of forming a channel layer of an electric device according to an embodiment is provided. First, a conductive substrate including an insulating layer on the substrate is provided. The conductive substrate and a metal to be plated are used as respective electrodes to carry out electroplating within an electrolyte solution. In this case, electrons provided by a tunneling current passing through the insulating layer from the conductive substrate are bonded with ions of the metal within the electrolyte solution to form a metal channel layer on the insulating layer.

Abstract: A binding enhancing apparatus according to the present invention includes: a first electrode; a second electrode spaced from the first electrode; a channel unit electrically connected at a portion with the first electrode and electrically connected at another portion with the second electrode; a stimuli source electrically connected with the channel unit and applying an electric stimulus; and probes connected to the channel unit and complementarily bound with target materials to sense.

Abstract: A reference potential adjusting apparatus is provided. The reference potential adjusting apparatus includes a reference potential measuring unit configured to measure a potential of a solution, a counter electrode disposed in the solution, and configured to change the potential of the solution through oxidation-reduction reactions with the solution, and a comparator configured to compare a measurement voltage provided by the reference voltage measuring unit to a reference voltage provided by a reference voltage supply unit, and to adjust reactions of the counter electrode with the solution according to the result of the comparison. The reference potential measuring unit includes a reference electrode, a common electrode disposed to be spaced apart from the reference electrode, and at least one nano structure contacting the reference electrode and the common electrode, and having electrical conductivity changing according to the potential of the solution.

Abstract: An apparatus includes a gasket disposed between a base and a flexible printed circuit bracket. A stiction between the gasket and flexible printed circuit bracket is greater than a stiction between the gasket and the base. The difference in stiction can be provided by differing materials and/or differing contact areas.

Abstract: The present invention relates to a system for and a method of manufacturing a linear gear (rack gear), in which a forming roll and a guide roll are used to form gear teeth in a sequential manner so as not to require a high load, thereby enabling to easily manufacture the rack gear. A system for manufacturing a rack gear according to the invention includes a forming roll having a convexo-concave portion formed on a part of the surface contacting with a linear bar, a guide roll adapted to roll while facing the forming roll, and at least one support member for supporting the linear bar so as to allow the linear bar to linearly move.

Abstract: In one embodiment, the antenna for inductively coupled plasma generation includes a first end connected to an alternating current (AC) power supply, a second end connected to a ground terminal, and an antenna coil unit connected to the first end and the second end and configured to generate an induced electric field when power of the AC power supply is applied. The antenna coil unit includes one or more sub-coil units. The one or more sub-coil units generate a magnetic field in a region adjacent to the antenna coil unit in response to the applied power.

Abstract: The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.

Abstract: Embodiments feature a sensor including a nanostructure and methods for manufacturing the same. In some embodiments, a sensor includes a substrate, a first electrode disposed on the substrate, and a second electrode disposed on the substrate. The second electrode is spaced apart from the first electrode and surrounding the first electrode. The sensor includes at least one nanostructure contacting the first electrode and the second electrode, in which the nanostructure is configured to vary an electrical characteristic according to an object to be sensed.

Abstract: Disclosed are a biomolecular sensor and a method of fabricating the same having high sensitivity and resolution by using a plurality of metal plates that change electrical properties of a plurality of nanostructures according to the attachment of biomolecules. The biomolecular sensor includes a substrate, first and second electrodes disposed to be spaced apart from each other on the substrate, a plurality of nanostructures disposed on the substrate to connect the first and second electrodes to each other, and a plurality of metal plates that change electrical properties of the plurality of nanostructures according to the attachment of biomolecules.

Abstract: The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.