Abstract: The present invention provides a flat fluorescent lamp. The flat fluorescent lamp comprises a single plate. Consequently, the flat fluorescent lamp is structurally safe, brightness of the flat fluorescent lamp is high, and efficiency of the flat fluorescent lamp is also high without the provision of other additional optical components. The present invention also provides a method of manufacturing such a flat fluorescent lamp.

Abstract: A ceramic multilayer substrate is formed by vertically stacking and firing a plurality of ceramic sheets, in which a connection bar is vertically formed between internal patterns and an external terminal of each ceramic sheet, preventing metallic conductive layers of the internal patterns from being deformed during processing the external terminal. The ceramic multilayer substrate has pattern layers formed on surfaces of at least some of the ceramic sheets. At least one through hole is formed on the edges of the stacked ceramic sheets so as to be opened to the outside. An external terminal is formed on an inner wall of the through hole connected with the pattern layers, and directly contacting the connection bar, whereby the connection bar supports the electrical connection between the external terminal and the pattern layers.

Abstract: A high-speed programmable ROM, a memory cell structure therefor, and a method for writing data on/reading data from the programmable ROM are provided.

Abstract: Disclosed are a precharge circuit employing an inactive weak precharging and equalizing scheme, a memory device including the same and a precharging method. The inactive weak precharging and equalizing scheme equalizes a non-selected bit line and complementary bit line while sensing and amplifying memory cell data delivered to a selected bit line and complementary bit line to evaluate the voltage difference between the selected bit line and complementary bit line. Then, the scheme precharges the selected bit line and complementary bit line and the non-selected bit line and complementary bit line. This does not require high precharge driving capability for inactivated bit line and complementary bit line equalized to a predetermined voltage level so that precharge current and operating current can be reduced.

Abstract: A multi-port semiconductor memory device includes a plurality of memory cells, each having a first bitline pair and a second bitline pair, and a plurality of flipped memory cells, each having a first flipped bitline pair and a second flipped bitline pair. The memory cells and the flipped memory cells are alternately arranged in a row direction, and a predetermined preparatory memory cell is arranged between the memory cell and the flipped memory cell that are adjacent to each other at a predetermined position in the row direction. In particular, the preparatory memory cell connects the first bitline pair of the memory cell to the second bitline pair of the flipped memory cell and connects the second bitline pair of the memory cell to the first bitline pair of the flipped memory cell.

Abstract: Disclosed herein is a portable digital communication device usable as a gaming device and a personal digital assistant. The device comprises a body housing, a center sliding housing for opening or closing a top surface of the body housing while being continuously opposite to the top surface of the body housing, and at least one side sliding housing attached to a side surface of the body housing and adapted to slide while being continuously opposite to the side surface of the body housing. The side sliding housing is arranged in parallel with the center sliding housing.

Abstract: A high speed programmable ROM, a memory cell structure therefor, and a method for writing data on/reading data from the programmable ROM are provided.

Abstract: Disclosed is a thermoplastic elastomer composition comprising 100 parts by weight of EPDM rubber, 5-1,000 parts by weight of styrenic thermoplastic elastomer, 50-3,000 parts by weight of paraffin oil, 10-200 parts by weight of a polyolefin resin as a curative, 1-15 parts by weight of a phenolic resin, and 0.5-5 parts by weight of a curing activator. The composition is superior in flowability, mechanical properties and oil resistance as well as being low in hardness, so that it can be applied for automobile parts.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: A memory cell structure of a metal (or via) programmable ROM whereby a transistor is shared between bit cells of the programmable ROM. Such a memory cell structure may include: a word line; a bit line; first and second virtual grounding lines; a grounding line; a first bit cell selected by signals of the word line and the first virtual grounding line; and a second bit cell selected by signals of the word line and the second virtual grounding line, wherein a cell transistor, one side of which is connected to the bit line is shared both by the first and second bit cells. Also, the other side of the cell transistor may be floated or connected to the bit line or, alternatively, connected to any one of the first virtual grounding line, the second virtual grounding line and the grounding line, and the gate of the cell transistor is connected to the word line.

Abstract: Disclosed are a ceramic multilayer substrate formed by vertically stacking and firing a plurality of ceramic substrates, in which a connection bar is longitudinally formed on connection areas between internal patterns and an external terminal of each ceramic substrate, thereby preventing metallic conductive layers of the internal patterns from being deformed during processing the external terminal and stably connecting the internal patterns to the external terminal, and a method for manufacturing the substrate.

Abstract: Step keys, a step key assembly, and a terminal having the step key assembly are disclosed. An individual step key includes a first slope portion inclined at a first predetermined angle, a second slope portion inclined at a second predetermined angle in the opposite direction to the first slope portion, a recess having a first height and opened under the first slope portion in the forward direction of the step key, a protrusion having a second height lower than the first height and extended from under the second slope portion in the rear direction of the step key, and an extension extended from under the first and second slope portions.

Abstract: A multi-port semiconductor memory device having a reduced bitline voltage offset and method for arranging memory cells so as to reduce the bitline voltage offset in a multi-port semiconductor memory device are provided. The multi-port semiconductor memory device incldues a plurality of memory cells, each having a first bitline pair and a second bitline pair, and a plurality of flipped memory cells, each having a first flipped bitline pair and a second flipped bitline pair. The memory cells and the flipped memory cells are alternately arranged in a row direction, and a predetermined preparatory memory cell is arranged between the memory cell and the flipped memory cell that are adjacent to each other at a predetermined position in the row direction. In particular, the preparatory memory cell connects the first bitline pair of the memory cell to the second bitline pair of the flipped memory cell and connects the second bitline pair of the memory cell to the first bitline pair of the flipped memory cell.

Abstract: Disclosed is a fringe field switching liquid crystal display capable of improving picture quality by minimizing vertical components in a fringe field.

Abstract: Disclosed is a mobile telephone terminal provided with a main housing having an antenna unit, a speaker unit, a LCD, a key array including a plurality of keys, and a microphone unit, and comprising (a) the main housing including a front end and at least one side end, and (b) a replaceable sub-housing including a front end, a first wing and a second wing extended from both side surfaces of the front end in the longitudinal direction, and an accommodation area disposed between the front end and the first and second wings, wherein the replaceable sub-housing surrounds a designated area of the main housing and is attached to and detached from the main housing in the longitudinal direction.

Abstract: Step keys, a step key assembly, and a terminal having the step key assembly are disclosed. An individual step key includes a first slope portion inclined at a first predetermined angle, a second slope portion inclined at a second predetermined angle in the opposite direction to the first slope portion, a recess having a first height and opened under the first slope portion in the forward direction of the step key, a protrusion having a second height lower than the first height and extended from under the second slope portion in the rear direction of the step key, and an extension extended from under the first and second slope portions.