Abstract: Many aspects of an IC package are disclosed. The IC package includes a substrate, an integrated circuit die, a vertical capacitor and a conductive layer. The substrate includes a first plurality of substrate pads. The integrated circuit die is coupled to the first plurality of substrate pads embedded in a first layer of the substrate. The vertical capacitor has a first electrode, a second electrode and a first resistive layer. The first electrode is coupled to the first resistive layer. The first resistive layer is coupled to a first substrate pad embedded in the first layer of the substrate. The conductive layer is formed over a first surface and the second electrode of the vertical capacitor. The conductive layer encapsulates the vertical capacitor. The first and second electrodes are parallel to each other and perpendicular to a planar surface of the substrate.

Abstract: Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.

Abstract: A semiconductor package according to some examples of the disclosure may include a first body layer, a transformer that may comprise one or more inductors, coupled inductors, or inductive elements positioned above the first body layer. A first ground plane is on a top of the first body layer between the first body layer and the inductive element. The first ground plane may have conductive lines generally perpendicular to a magnetic field generated by the inductive element, and a second ground plane on a bottom of the first body layer opposite the first ground plane. The first and second ground planes may also provide heat dissipation elements for the semiconductor as well as reduce or eliminate eddy current and parasitic effects produced by the inductive element.

Abstract: A passive discrete device may include a first asymmetric terminal and a second asymmetric terminal. The passive discrete device may further include first internal electrodes extended to electrically couple to a first side and a second side of the first asymmetric terminal. The passive discrete device may also include second internal electrodes extended to electrically couple to a first side and a second side of the second asymmetric terminal.

Abstract: A package on package structure may be formed by fabricating or providing a bottom package having a substrate, at least one die on top of the substrate, and bonding pads on the top of the substrate. Next, a frame is formed on the bonding pads and connected to the bonding pads. Next, a package material is molded over the top of the substrate to encapsulate the frame, the die, and the pads or substantially encapsulates these components. Next, a portion of the molded package material is removed to expose at least a portion of the frame. The exposed frame portions are formed such that a desired fan in or fan out configuration is obtained. Next, a non-conductive layer is formed on the exposed frame. Last, a second package having a die or chip is connected to the exposed portion of the frame to form a package on package structure.

Abstract: An embedded layered inductor is provided that includes a first inductor layer and a second inductor layer coupled to the first inductor layer. The first inductor layer comprises a patterned metal layer that may also be patterned to form pads. The second inductor layer comprises metal deposited in a dielectric layer adjacent the patterned metal layer.

Abstract: Embodiments contained in the disclosure provide a method and apparatus for testing an electronic device. An electronic device is installed in a test socket guide. A pusher tip applies a load to the guided coaxial spring probes and forces contact with pads on the device. Test and ground signals are routed through the device and test socket. The apparatus includes a socket having at least one guided coaxial spring probe pin. A socket guide shim is positioned between the receptacle for the electronic device and the socket. A socket guide aids positioning. A pusher tip is placed on the side opposite that of the guided coaxial spring probe pins. The pusher tip mates with a pusher shim and the pusher spring. A top is then placed on the assembly and acts to compress the pusher spring and engage the guided coaxial spring probe pins with the pads on the device.

Abstract: The present disclosure provides semiconductor packages and methods for fabricating PoP semiconductor packages.

Abstract: Low inductance to ground can be provided in wire-bond based device packages. An example device package may include a die on a package substrate, a mold on the package substrate and encapsulating the die, an upper ground conductor on the mold, and ground wire bonds within the mold. The die may include a plurality of terminals on an upper surface of the die. The plurality of ground wire bonds may electrically couple the die and the upper ground conductor. For each ground wire bond, a first end of that ground wire bond may be configured to electrically couple to a corresponding terminal on the upper surface of the die and a second end of that ground wire bond may be configured to electrically couple to the upper ground conductor at the upper surface of the mold.

Abstract: A flip-chip employing an integrated cavity filter is disclosed comprising an integrated circuit (IC) chip comprising a semiconductor die and a plurality of conductive bumps. The plurality of conductive bumps is interconnected to at least one metal layer of the semiconductor die to provide a conductive “fence” that defines an interior resonator cavity for providing an integrated cavity filter in the flip-chip. The interior resonator cavity is configured to receive an input RF signal from an input transmission line through an input signal transmission aperture provided in an internal layer in the semiconductor die. The interior resonator cavity resonates the input RF signal to generate the output RF signal comprising a filtered RF signal of the input RF signal, and couples the output RF signal on an output signal transmission line in the flip-chip through an output transmission aperture provided in the aperture layer.

Abstract: Some implementations provide an integrated device (e.g., semiconductor device) that includes a substrate and an inductor in the substrate. In some implementations, the inductor is a solenoid inductor. The inductor includes a set of windings. The set of windings has an inner perimeter. The set of windings includes a set of interconnects and a set of vias. The set of interconnects and the set of vias are located outside the inner perimeter of the set of windings. In some implementations, the set of windings further includes a set of capture pads. The set of interconnects is coupled to the set of vias through the set of capture pads. In some implementations, the set of windings has an outer perimeter. The set of pads is coupled to the set of interconnects such that the set of pads is at least partially outside the outer perimeter of the set of windings.

Abstract: A substrate that includes a first dielectric layer and a capacitor embedded in the first dielectric layer. The capacitor includes a first terminal, a second terminal, and a third terminal. The second terminal is laterally located between the first terminal and the third terminal. The capacitor also includes a second dielectric layer, a first metal layer and a second metal layer. The first metal layer is coupled to the first and third terminals. The first metal layer, the first terminal, and the third terminal are configured to provide a first electrical path for a first signal. The second metal layer is coupled to the second terminal. The second metal layer and the second terminal are configured to provide a second electrical path for a second signal.

Abstract: Some features pertain to a package substrate that includes at least one dielectric layer, an inductor in the at least one dielectric layer, a first terminal coupled to the inductor, a second terminal coupled to the inductor, and a third terminal coupled to the inductor. The first terminal is configured to be a first port for the inductor. The second terminal is configured to be a second port for the inductor. The third terminal is a dummy terminal. In some implementations, the package substrate includes a solder resist layer over the dielectric layer, where the solder resist layer covers the third terminal. In some implementations, the package substrate includes a solder interconnect over the third terminal, such that the solder resist layer is between the third terminal and the solder interconnect. In some implementations, the package substrate is coupled to a die comprising a plurality of switches.

Abstract: Some features pertain to a device package that includes a die and a package substrate. The die includes a first switch. The package substrate is coupled to the die. The package substrate includes at least one dielectric layer, a primary inductor, and a first secondary inductor coupled to the first switch of the die. The first secondary inductor and the first switch are coupled to a plurality of interconnects configured to provide an electrical path for a reference ground signal. The primary inductor is configurable to have different inductances by opening and closing the first switch coupled to the first secondary inductor. In some implementations, the primary inductor is configurable in real time while the die is operational. In some implementations, the die further includes a second switch, and the package substrate further includes a second secondary inductor coupled to the second switch of the die.

Abstract: An integrated radio frequency (RF) circuit structure may include a resistive substrate material and a switch. The switch may be arranged in a silicon on insulator (SOI) layer supported by the resistive substrate material. The integrated RF circuit structure may also include an isolation layer coupled to the SOI layer. The integrated RF circuit structure may further include a filter, composed of inductors and capacitors. The filter may be arranged on a surface of the integrated RF circuit structure, opposite the resistive substrate material. In addition, the switch may be arranged on a first surface of the isolation layer.

Abstract: A multi-layer ground shield structure of interconnected elements is disclosed. The ground shield structure may include a first patterned layer of a ground shield structure, a second patterned layer of the ground shield structure, and a spacer between the first patterned layer and the second patterned layer. The first patterned layer includes first conductive elements interconnected within the first patterned layer according to a first pattern. The second patterned layer includes second conductive elements interconnected within the second patterned layer according to a second pattern.

Abstract: An integrated circuit device that includes a package substrate and a die coupled to the package substrate. The package substrate includes at least one dielectric layer, a first stack of first interconnects in the at least one dielectric layer, and a second interconnect formed on at least one side portion of the at least one dielectric layer. The first stack of first interconnects is configured to provide a first electrical path for a non-ground reference signal, where the first stack of first interconnects is located along at least one side of the package substrate. The second interconnect is configured to provide a second electrical path for a ground reference signal.

Abstract: A package substrate that includes a first portion and a redistribution portion. The first portion is configured to operate as a capacitor. The first portion includes a first dielectric layer, a first set of metal layers in the dielectric layer, a first via in the dielectric layer, a second set of metal layers in the dielectric layer, and a second via in the dielectric layer. The first via is coupled to the first set of metal layers. The first via and the first set of metal layers are configured to provide a first electrical path for a ground signal. The second via is coupled to the second set of metal layers. The second via and the second set of metal layers are configured to provide a second electrical path for a power signal. The redistribution portion includes a second dielectric layer, and a set of interconnects.

Abstract: An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

Abstract: Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.