Abstract: Disclosed herein is an electronic component package including: a connection member provided on at least one surface of a substrate; an active element coupled to the substrate by the connection member; a molding part covering an exposed surface of the active element; and an additional layer formed on an exposed surface of the molding part to decrease a warpage phenomenon. In the electronic component package, the warpage phenomenon may be decreased as compared with the related art.

Abstract: Disclosed herein are a system of measuring a warpage and a method of measuring a warpage. The system of measuring a warpage of a sample by analyzing an image photographed by the camera using light that is diffused from a light source and reflected on a surface of a sample and is arrived at the camera through a reference grating part, the system includes: an intake part that removes a fume generated from the sample. By this configuration, it is possible to measure the warpage while effectively removing the fume generated from the sample according to the increase in the temperature of the sample at the time of measuring the warpage, thereby improving the accuracy of the warpage measurement.

Abstract: There is provided a linear vibrator, including: a fixed part providing an interior space having a predetermined size; at least one magnet disposed in the interior space and generating magnetic force; a vibration part including a coil facing the magnet and generating electromagnetic force through interaction with the magnet and a mass body; and an elastic member coupled to the fixed part and the vibration part to mediate vibrations of the vibration part and having a damping increasing portion attached to a predetermined region of a surface thereof.

Abstract: Disclosed herein are a semiconductor chip package and a manufacturing method thereof. The manufacturing method of the semiconductor chip package includes: a) mounting a semiconductor chip on a printed circuit board (PCB); b) inserting a warpage suppressing reinforcement member into an inner ceiling of a mold manufactured in order to package the PCB having the semiconductor chip mounted thereon; c) combining the mold having the warpage suppressing reinforcement member inserted into the ceiling thereof with the upper surface of the PCB so as to surround the PCB having the semiconductor chip mounted thereon; d) injection-molding and filling a molding material in the mold, and hardening the molding material by applying heat, and e) hardening the molding material and then removing the mold to complete the semiconductor chip package.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming semiconductor patterns on a semiconductor substrate, such that sides are surrounded by a lower interlayer insulating layer. A lower insulating layer is formed that covers the semiconductor patterns and the lower interlayer insulating layer. A contact structure is formed that penetrates the lower insulating layer and the lower interlayer insulating layer and is spaced apart from the semiconductor patterns. The contact structure has an upper surface higher than the semiconductor patterns. An upper insulating layer is formed covering the contact structure and the lower insulating layer. The upper and lower insulating layers form insulating patterns exposing the semiconductor patterns and covering the contact structure, and each of the insulating patterns includes a lower insulating pattern and an upper insulating pattern sequentially stacked.

Abstract: There is provided a linear vibrator, including: a fixed part providing an interior space having a predetermined size; at least one magnet disposed in the interior space and generating magnetic force; a vibration part including a coil facing the magnet and generating electromagnetic force through interaction with the magnet and a mass body; and an elastic member coupled to the fixed part and the vibration part to mediate vibrations of the vibration part and having a damping increasing portion attached to a predetermined region of a surface thereof.

Abstract: Integrated circuit memory devices include a semiconductor word line having an electrically insulating strain layer directly contacting an upper surface thereof. The strain layer, which has a contact opening therein, has a sufficiently high degree of internal compressive strain therein to thereby impart a net tensile stress within at least a first portion of the semiconductor word line. A P-N junction diode is also provided on the semiconductor word line. The diode includes a first terminal (e.g., cathode, anode) electrically coupled through the opening in the strain layer to the surface of the semiconductor word line. A data storage element (e.g., MRAM, FRAM, PRAM, RRAM, etc.) may also be provided, which has a current carrying terminal electrically coupled to a second terminal of the p-n junction diode.

Abstract: A multi-bit phase change memory device including a phase change material having a plurality of crystalline phases. A non-volatile multi-bit phase change memory device may include a phase change material in a storage node, wherein the phase change material includes a binary or ternary compound sequentially having at least three crystalline phases having different resistance values according to an increase of temperature of the phase change material.

Abstract: Integrated circuit memory devices include a semiconductor word line having an electrically insulating strain layer directly contacting an upper surface thereof. The strain layer, which has a contact opening therein, has a sufficiently high degree of internal compressive strain therein to thereby impart a net tensile stress within at least a first portion of the semiconductor word line. A P-N junction diode is also provided on the semiconductor word line. The diode includes a first terminal (e.g., cathode, anode) electrically coupled through the opening in the strain layer to the surface of the semiconductor word line. A data storage element (e.g., MRAM, FRAM, PRAM, RRAM, etc.) may also be provided, which has a current carrying terminal electrically coupled to a second terminal of the p-n junction diode.

Abstract: A phase-change memory device has an oxidation barrier layer to protect against memory cell contamination or oxidation. In one embodiment, a semiconductor memory device includes a molding layer disposed over semiconductor substrate, a phase-changeable material pattern, and an oxidation barrier of electrically insulative material. The molding layer has a protrusion at its upper portion. One portion of the phase-changeable material pattern overlies the protrusion of the molding layer, and another portion of the phase-changeable material pattern extends through the protrusion. The electrically insulative material of the oxidation barrier may cover the phase-changeable material pattern and/or extend along and cover the entire area at which the protrusion of the molding layer and the portion of the phase-change material pattern disposed on the protrusion adjoin.

Abstract: A variable resistance memory device includes a memory cell connected to a bit line and a clamp circuit configured to provide either a first read voltage or a second read voltage to the bit line according to an elapsed time from a write operation of the memory cell. Related methods are also described.

Abstract: In a method of forming a phase-change memory device, a variable resistance member may be formed on a s semiconductor substrate having a contact region, and a first electrode may be formed to contact a first portion of the variable resistance member and to be electrically connected to the contact region. A second electrode may be formed so as to contact a second portion of the variable resistance member.

Abstract: A composite sheet used for artificial leather with low elongation and excellent softness which includes a non-woven fabric layer, a woven or knitted fabric layer and a polyurethane resin, wherein the non-woven fabric layer and the woven or knitted fabric layer are entangled with each other.

Abstract: Provided is a method of manufacturing a nanowire capacitor including forming a lower metal layer on a substrate; growing conductive nanowires on the lower metal layer, the conductive nanowires including metal and transparent electrodes; depositing a dielectric layer on the lower metal layer including the grown conductive nanowires; growing dielectric nanowires on the deposited dielectric layer; and depositing an upper metal layer on the dielectric layer including the grown dielectric nanowires.

Abstract: A composite sheet used for artificial leather with low elongation and excellent softness which includes a non-woven fabric layer, a woven or knitted fabric layer and a polyurethane resin, wherein the non-woven fabric layer and the woven or knitted fabric layer are entangled with each other.

Abstract: A multi-bit phase change memory device including a phase change material having a plurality of crystalline phases. A non-volatile multi-bit phase change memory device may include a phase change material in a storage node, wherein the phase change material includes a binary or ternary compound sequentially having at least three crystalline phases having different resistance values according to an increase of temperature of the phase change material.

Abstract: There are provided a semiconductor light emitting device using a phosphor film formed on a nanowire structure and a method of manufacturing the device, the device including: a substrate; a light emitting structure including a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer sequentially formed on the substrate; a plurality of nanowire structures formed on the light emitting structure and formed of a transparent material; and a phosphor film formed on at least an upper surface and a side surface of each of the plurality of nanowire structures.

Abstract: A phase changeable random access memory (PRAM) and methods for manufacturing the same. An example unit cell of a non-volatile memory, such as a PRAM, includes a MOS transistor, connected to an address line and a data line, where the MOS transistor receives a voltage from the data line. The unit cell further includes a phase change material for changing phase depending on heat generated by the voltage and a top electrode, connected to a substantially ground voltage.

Abstract: A non-volatile memory device may include a plurality of data cells, each data cell of the plurality of data cells programmed to have a first resistance variation among a plurality of first resistance variations; and a plurality of reference cells, each reference cell of the plurality of reference cells programmed to have a second resistance variation among a plurality of second resistance variations. A change in a resistance of the data cells is used to identify a level of data programmed to memory. Because the resistance variation of the data cells may change with time or due to changes in temperature, a reference cell is also included in the non-volatile memory device. The reference cell is used for effective reading of the data value of a corresponding data cell. A storage system may include the non-volatile memory device.

Abstract: Provided is a laminated ceramic substrate. The laminated ceramic substrate includes a first ceramic layer, a second ceramic layer, and a third ceramic layer. The first ceramic layer is formed of a material with a first thermal expansion coefficient. The second ceramic layer is laminated on one side of the first ceramic layer. The second ceramic layer is formed of a material with a second thermal expansion coefficient different from the first thermal expansion coefficient. The third ceramic layer is laminated on the other side of the first ceramic layer. The third ceramic layer is formed of a material with the second thermal expansion coefficient. The third ceramic layer has a different thickness than the second ceramic layer.