Abstract: The present invention relates to a composition for detecting phosphatase or kinase activity and a method of detecting phosphatase or kinase activity. The kinase or phosphatase activity may be quantitatively measured in real time by using the composition of the present invention.

Abstract: An antifreeze member includes a metal substrate, and a first coating layer including a recombinant antifreeze protein in which a metal-binding protein is conjugated to a performance-enhancing reformed antifreeze protein, and being bonded to the metal substrate via the metal-binding protein.

Abstract: The present invention relates to a fragment antigen-binding (Fab) fragment specifically binding to epidermal growth factor receptor (EGFR), an expression construct for preparing the Fab fragment, a method for preparing the Fab fragment, and a pharmaceutical composition containing the Fab fragment. The Fab fragment to EGFR of the present invention is smaller than the antibody, and thus can favorably permeate into tissues or tumors and can be prepared in bacteria, resulting in low production costs. Furthermore, the Fab fragment to EGFR of the present invention has an increased in vivo half-life through pegylation.

Abstract: Systems and methods for low latency acquisition of soft data from a memory cell based on a sensing time and/or a leakage current are described. In one embodiment, the systems and methods may include applying a first read voltage to a word line of a page of memory cells selected by a processor of a flash memory device for a read operation, applying a pass voltage to word lines associated with one or more different pages of memory cells of the memory block, upon applying the first read voltage sensing whether a bit line of a memory cell in the selected page conducts, measuring a side effect associated with sensing whether the bit line of the memory cell in the selected page conducts, and assigning a LLR value to the memory cell as a soft LDPC input based at least in part on the measured side effect.

Abstract: Systems and methods for low latency acquisition of soft data from a memory cell based on a sensing time and/or a leakage current are described. In one embodiment, the systems and methods may include applying a first read voltage to a word line of a page of memory cells selected by a processor of a flash memory device for a read operation, applying a pass voltage to word lines associated with one or more different pages of memory cells of the memory block, upon applying the first read voltage sensing whether a bit line of a memory cell in the selected page conducts, measuring a side effect associated with sensing whether the bit line of the memory cell in the selected page conducts, and assigning a LLR value to the memory cell as a soft LDPC input based at least in part on the measured side effect.

Abstract: The disclosed technology provides for multi-dimensional data randomization in a memory cell array using circular shifts of an initial scrambling sequence. Data addressed to a first row of a data array is randomized using the initial scrambling sequence and data addressed to each row of the memory cell array is randomized using a scrambling sequence that is equal to a circular shift of the initial sequence.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a block of solid-state non-volatile memory cells are each programmed to an associated programmed state responsive to a respective amount of accumulated charge. A charge loss compensation circuit adds a relatively small amount of additional charge to the respective amount of accumulated charge in each of the memory cells to maintain the associated programmed states of the cells.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a block of solid-state non-volatile memory cells are each programmed to an associated programmed state responsive to a respective amount of accumulated charge. A charge loss compensation circuit adds a relatively small amount of additional charge to the respective amount of accumulated charge in each of the memory cells to maintain the associated programmed states of the cells.

Abstract: Herein, there is disclosed an LED illuminator installed to illuminate an inner space of a hood of a vehicle when the hood is open. The LED illuminator comprises a protection frame positioned in an inner space of the hood; and an LED module having a light emitting portion, wherein the light emitting portion is installed to be concealed into and exposed to the outside of the protection frame.

Abstract: Methods and systems that include receiving data to be written to a NAND array in a controller; and writing the data to the NAND array, the NAND array including both type A NAND cells and type B NAND cells, wherein the type A NAND cells and the type B NAND cells have at least one structural difference.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with various embodiments, a first data access operation is conducted on a memory cell and a first temperature associated with the memory cell and associated with the first data access operation is measured. A second temperature associated with the memory cell is measured. At least one operational parameter is adjusted responsive to the first and second temperatures associated with the memory cell. A second data access operation is conducted on the memory cell using the adjusted operational parameter.

Abstract: The disclosed technology provides for multi-dimensional data randomization in a memory cell array using circular shifts of an initial scrambling sequence. Data addressed to a first row of a data array is randomized using the initial scrambling sequence and data addressed to each row of the memory cell array is randomized using a scrambling sequence that is equal to a circular shift of the initial sequence.

Abstract: Methods and systems that include receiving data to be written to a NAND array in a controller; and writing the data to the NAND array, the NAND array including both type A NAND cells and type B NAND cells, wherein the type A NAND cells and the type B NAND cells have at least one structural difference.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with various embodiments, a first data access operation is conducted on a memory cell and a first temperature associated with the memory cell and associated with the first data access operation is measured. A second temperature associated with the memory cell is measured. At least one operational parameter is adjusted responsive to the first and second temperatures associated with the memory cell. A second data access operation is conducted on the memory cell using the adjusted operational parameter.

Abstract: Provided is a semiconductor device. The semiconductor device includes a fin on a substrate; a gate electrode cross the fin on the substrate; a source/drain formed on at least one of both sides of the gate electrode, and including a first film and a second film; and a stress film arranged between an isolation film on the substrate and the source/drain, and formed on a side surface of the fin.

Abstract: An antifreeze member includes a metal substrate, and a first coating layer including a recombinant antifreeze protein in which a metal-binding protein is conjugated to a performance-enhancing reformed antifreeze protein, and being bonded to the metal substrate via the metal-binding protein.

Abstract: Threshold voltage offsets for threshold voltages are determined. The threshold voltage offsets may be linearly related by a non-zero slope. The threshold voltages are shifted using their respective threshold voltage offsets. The threshold voltages that are shifted by their respective threshold voltage offsets are used to read data from multi-level memory cells.

Abstract: A first page in a memory unit is programmed with one or more pages of the secondary memory. A first time corresponding to the start of the programming of the first page is recorded. A second time corresponding to the completion of the programming of the one or more pages is recorded. A time difference between the first time and the second time is determined. It is determined if the time difference is greater than a threshold. In response to the time difference being greater than the threshold, a retention based defecting process is for the memory unit is disabled.

Abstract: A first page in a memory unit is programmed with one or more pages of the secondary memory. A first time corresponding to the start of the programming of the first page is recorded. A second time corresponding to the completion of the programming of the one or more pages is recorded. A time difference between the first time and the second time is determined. It is determined if the time difference is greater than a threshold. In response to the time difference being greater than the threshold, a retention based defecting process is for the memory unit is disabled.

Abstract: A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.